SBVS037P August   2003  – December 2015 TPS732

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Output Noise
      2. 7.3.2 Internal Current Limit
      3. 7.3.3 Enable Pin and Shutdown
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Reverse Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation With 1.7 V ≤ VIN ≤ 5.5 V and VEN ≥ 1.7 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VIN –0.3 6 V
VEN –0.3 6
VOUT –0.3 5.5
VNR, VFB –0.3 6
Peak output current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Power Dissipation
Temperature Junction range ,TJ –55 150 °C
Storage range, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VIN Input supply voltage range 1.7 5.5 V
IOUT Output current 0 250 mA
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS732(3) UNIT
DRB [SON] DCQ [SOT223] DBV [SOT23]
8 PINS 6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 58.3 53.1 205.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.8 35.2 119
RθJB Junction-to-board thermal resistance 72.8 7.8 35.4
ψJT Junction-to-top characterization parameter 2.7 2.9 12.7
ψJB Junction-to-board characterization parameter 25 7.7 34.5
RθJC(bot) Junction-to-case (bottom) thermal resistance 5 N/A N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
  1. i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.        
    . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3 × 2 thermal via array.        
    . iii. DBV: There is no exposed pad with the DBV package.      
  2. i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.    
    . ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.        
    . iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
  3. These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.

6.5 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V(1), IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 1.7 5.5 V
VFB Internal reference (TPS73201) TJ = 25°C 1.198 1.2 1.21 V
VOUT Output voltage range (TPS73201)(2) VFB 5.5 – VDO V
Accuracy(1)(3) Nominal TJ = 25°C –0.5% 0.5%
VIN, IOUT, and T VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 250 mA		 –1% ±0.5% 1%
ΔVOUT(ΔVIN) Line regulation(1) VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V 0.01 %/V
ΔVOUT(ΔIOUT) Load regulation 1 mA ≤ IOUT ≤ 250 mA 0.002 %/mA
10 mA ≤ IOUT ≤ 250 mA 0.0005 %/mA
VDO Dropout voltage(4)
(VIN = VOUT (nom) – 0.1 V)		 IOUT = 250 mA 40 150 mV
ZO(do) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO 0.25 Ω
ICL Output current limit VOUT = 0.9 × VOUT(nom) 250 425 600 mA
ISC Short-circuit current VOUT = 0 V 300 mA
IREV Reverse leakage current(5) (–IIN) VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT 0.1 10 μA
IGND GND pin current IOUT = 10 mA (IQ) 400 550 μA
IOUT = 250 mA 650 950
ISHDN Shutdown current (IGND) VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5,
–40°C ≤ TJ ≤ 100°C		 0.02 1 µA
IFB FB pin current (TPS73201) 0.1 0.3 μA
PSRR Power-supply rejection ratio
(ripple rejection)		 f = 100 Hz, IOUT = 250 mA 58 dB
f = 10 kHz, IOUT = 250 mA 37
Vn Output noise voltage
BW = 10Hz – 100kHz		 COUT = 10 μF, No CNR 27 × VOUT μVRMS
COUT = 10 μF, CNR = 0.01 μF 8.5 × VOUT
VEN(high) EN pin high (enabled) 1.7 VIN V
VEN(low) EN pin low (shutdown) 0 0.5 V
IEN(high) EN pin current (enabled) VEN = 5.5 V 0.02 0.1 μA
TSD Thermal shutdown temperature Shutdown Temp increasing 160 °C
Reset Temp decreasing 140
TJ Operating junction temperature –40 125 °C
(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
(2) TPS73201 is tested at VOUT = 2.5 V.
(3) Tolerance of external resistors not included in this specification.
(4) VDO is not measured for fixed output versions with VOUT(nom) < 1.8 V because minimum VIN = 1.7 V.
(5) Fixed-voltage versions only; refer to Application Information section for more information.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTR Start-up time VOUT = 3 V, RL = 30 Ω
COUT = 1 μF, CNR = 0.01 μF		 600 μs

6.7 Typical Characteristics

For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise noted.
TPS732 ld_reg_bvs037.gif
Figure 1. Load Regulation
TPS732 vdo_v_io_bvs037.gif
Figure 3. Dropout Voltage vs Output Current
TPS732 vo_shto_bvs037.gif
Figure 5. Output Voltage Accuracy Histogram
TPS732 ignd_v_io_bvs037.gif
Figure 7. Ground Pin Current vs Output Current
TPS732 ignd2_v_ta_bvs037.gif
Figure 9. Ground Pin Current in Shutdown vs Temperature
TPS732 ilimit_v_vi_bvs037.gif
Figure 11. Current Limit vs VIN
TPS732 psrr_v_f_bvs037.gif
Figure 13. PSRR (Ripple Rejection) vs Frequency
TPS732 noise_dnsty_bvs037.gif
Figure 15. Noise Spectral Density CNR = 0 µF
TPS732 vn_v_co_bvs037.gif
Figure 17. RMS Noise Voltage vs COUT
TPS732 load_tr_bvs037.gif
Figure 19. TPS73233 Load Transient Response
TPS732 trn-on_res_bvs037.gif
Figure 21. TPS73233 Turnon Response
TPS732 pw-up_pw-dn_bvs037.gif
Figure 23. TPS73233 Power Up and Power Down
TPS732 vn_v_cbf_bvs037.gif
Figure 25. TPS73201 RMS Noise Voltage vs CFB
TPS732 ldtrns_adj_bvs037.gif
Figure 27. TPS73201 Load Transient, Adjustable Version
TPS732 line_reg_bvs037.gif
Figure 2. Line Regulation
TPS732 vdo_v_ta_bvs037.gif
Figure 4. Dropout Voltage vs Temperature
TPS732 vo_hsto_dft_bvs037.gif
Figure 6. Output Voltage Drift Histogram
TPS732 ignd_v_ta_bvs037.gif
Figure 8. Ground Pin Current vs Temperature
TPS732 tc_ilim_fdbk_vout_bvs037.gif
Figure 10. Current Limit vs VOUT (Foldback)
TPS732 ililit_v_ta_bvs037.gif
Figure 12. Current Limit vs Temperature
TPS732 tc_psrr_vin_vout_bvs037.gif
Figure 14. PSRR (Ripple Rejection) vs (VIN – VOUT)
TPS732 noise2_dnsty_bvs037.gif
Figure 16. Noise Spectral Density CNR = 0.01 µF
TPS732 vn_cnr_bvs037.gif
Figure 18. RMS Noise Voltage vs CNR
TPS732 line_tr_bvs037.gif
Figure 20. TPS73233 Line Transient Response
TPS732 trn-off_res_bvs037.gif
Figure 22. TPS73233 Turnoff Response
TPS732 ienab_v_ta_bvs037.gif
.
Figure 24. IENABLE vs Temperature
TPS732 ifb_v_ta_bvs037.gif
Figure 26. TPS73201 IFB vs Temperature
TPS732 lntrns_adj_bvs037.gif
Figure 28. TPS73201 Line Transient, Adjustable Version