SBVS067R January   2006  – December 2019 TPS737

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Output Noise
      2. 7.3.2 Internal Current Limit
      3. 7.3.3 Enable Pin and Shutdown
      4. 7.3.4 Reverse Current
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Dropout Voltage
        3. 8.2.2.3 Transient Response
      3. 8.2.3 Application Curves
    3. 8.3 What To Do and What Not To Do
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation
      2. 10.1.2 Thermal Protection
      3. 10.1.3 Estimating Junction Temperature
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Noise

A precision bandgap reference is used to generate the internal reference voltage, Vref. This reference is the dominant noise source within the TPS737xx and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

Equation 1. TPS737 q_vn_32-bvs067.gif

Because the value of VR is 1.2 V, this relationship reduces to:

Equation 2. TPS737 q_vn_27-bvs067.gif

for the case of no CNR.

An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship:

Equation 3. TPS737 q_vn_8_5vrm-bvs038.gif

for CNR = 10 nF.

This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.

The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improve load transient performance. This capacitor should be limited to 0.1 µF.

The TPS737xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of switching noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT.