SBVS066R December   2005  – April 2017 TPS74401


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable, Shutdown
      2. 7.3.2 Power-Good (VQFN Package Only)
      3. 7.3.3 Internal Current Limit
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Transient Response
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Setting the TPS74401
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 Using an Auxiliary Bias Rail
      3. 8.2.3 Without an Auxiliary Bias
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Evaluation Modules
        2. Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, connect the capacitance on IN and BIAS as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve optimal transient performance and accuracy, connect the top side of R1 in Figure 27 as close as possible to the load. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turn-on response.

Layout Example

TPS74401 20_RGW_Layout.gif Figure 40. Layout Schematic (VQFN Packages)

Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions, and can be calculated using Equation 5:

Equation 5. TPS74401 q_pd_bvs066.gif

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the VQFN (RGW, RGR) packages, the primary conduction path for heat is through the exposed pad to the PCB. The pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On the DDPAK (KTW) package, the primary conduction path for heat is through the tab to the PCB. Connect that tab to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be estimated using Equation 6:

Equation 6. TPS74401 q_rja_bvs066.gif

Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 41.

TPS74401 tc_theta_ja_pcb_size_bvs066.gif


θJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 41. θJA versus Board Size

Figure 41 shows the variation of θJA as a function of ground plane copper area in the board. Figure 41 is intended only as a guideline to demonstrate the affects of heat spreading in the ground plane; do not use Figure 41 to estimate actual thermal performance in real application environments.


When the device is mounted on an application PCB, TI strongly recommends using ΨJT and ΨJB, as explained in the section.

Thermal Considerations

A better method of estimating the thermal measure comes from using the thermal metrics ΨJT and ΨJB, as shown in Thermal Information . These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than RθJA. The junction temperature can be estimated with the corresponding formulas given in Equation 7.

Equation 7. TPS74401 q_new_metrics_bvs066.gif


  • PD is the power dissipation shown by Equation 5,
  • TT is the temperature at the center-top of the IC package, and
  • TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (see Figure 42).


Both TT and TB can be measured on actual application boards using a thermo‐gun (an infrared thermometer).

For more information about measuring TT and TB, see the application note Using New Thermal Metrics (SBVA025), available for download at

TPS74401 ai_thermal_measmt_bvs064.gif
TT is measured at the center of both the X- and Y-dimensional axes.
TB is measured below the package lead on the PCB surface.
Figure 42. Measuring Points for TT and TB

Compared with θJA, the thermal metrics ΨJT and ΨJB are less independent of board size, but do have a small dependency on board size and layout. Figure 43 shows characteristic performance of ΨJT and ΨJB versus board size.

Referring to Figure 43, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point symmetric to an IC center. In the KTW package, for example (see Figure 42), silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a dependency. Also, because of that non-point symmetry, device heat distribution on the PCB is not point symmetric either, so that ΨJB has a greater dependency on board size and layout.

TPS74401 tc_psi_jt_jb_pcb_size_bvs066.gif Figure 43. ΨJT and ΨJB versus Board Size

For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to the application note Using New Thermal Metrics (SBVA025), available for download at Also, refer to the application note IC Package Thermal Metrics (SPRA953) (also available on the TI website) for further information.