SBVS099G November 2007 – October 2015 TPS74701
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, connect the capacitance on IN, OUT and BIAS as close as possible to the device. If BIAS is connected to IN, connect BIAS as close to the input supply as possible. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turnon response.
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve optimal transient performance and accuracy, the top side of R1 in Figure 25 should be connected as close as possible to the load. If BIAS is connected to IN, TI recommends connecting BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turnon response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4:
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.
On the SON (DRC) package, the primary conduction path for heat is through the exposed pad to the printed-circuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5:
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 29.
NOTE:θJA value at board size of 9in2 (that is, 3 inches × 3 inches) is a JEDEC standard.
Figure 29 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.
When the device is mounted on an application PCB, TI strongly recommends using ΨJT and ΨJB, as explained in the section.
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top parameter is listed as well.
Both TT and TB can be measured on actual application boards using a thermo‐gun (an infrared thermometer).
By looking at Figure 30, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size.
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, see application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, see application report SPRA953, Semiconductor and IC Package Thermal Metrics, also available on the TI website.