10.1 Layout Guidelines

An optimal layout can greatly improve transient performance, PSR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the top side of R₁ in Figure 24 should be connected as close as possible to the load. If BIAS is connected to IN, it is recommended to connect BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turnon response.

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 6:

Equation 6.

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On both the VSON (DRC) and QFN (RGW) packages, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 7:

Equation 7.

Knowing the maximum R_θJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 36.

NOTE:

θ_JA value at board size of 9 in² (that is, 3 in × 3i n) is a JEDEC standard.

Figure 36. Θ_JA vs Board Size

Figure 36 shows the variation of θ_JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.

10.2 Layout Example

Figure 37. Layout Example (RGW Package)

10.3 Estimating Junction Temperature

Using the thermal metrics Ψ_JT and Ψ_JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 8). For backwards compatibility, an older θ_JC,Top parameter is listed as well.

Equation 8.

Where P_D is the power dissipation shown by Equation 6, T_T is the temperature at the center-top of the IC package, and T_B is the PCB temperature measured 1 mm away from the IC package on the PCB surface (Figure 38).

For more information about measuring T_T and T_B, see the Using New Thermal Metrics application note, available for download at www.ti.com.

Figure 38. Measuring Points for T_T and T_B

By looking at Figure 39, the new thermal metrics (Ψ_JT and Ψ_JB) have very little dependency on board size. That is, using Ψ_JT or Ψ_JB with Equation 8 is a good way to estimate T_J by simply measuring T_T or T_B, regardless of the application board size.

Figure 39. Ψ_JT and Ψ_JB vs Board Size

For a more detailed discussion of why TI does not recommend using θ_JC(top) to determine thermal characteristics, see the Using New Thermal Metrics application report, available for download at www.ti.com. For further information, see the IC Package Thermal Metrics application report, also available on the TI website.