SBVS074L January   2007  – March 2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics IOUT = 50 mA
    7. 6.7 Typical Characteristics IOUT = 1 A
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable/Shutdown
      2. 7.3.2 Power Good
      3. 7.3.3 Internal Current Limit
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

At TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND.(1)
MIN MAX UNIT
Input voltage VIN, VBIAS –0.3 6 V
Enable voltage VEN –0.3 6 V
Power good voltage VPG –0.3 6 V
PG sink current IPG 0 1.5 mA
Soft-start voltage VSS –0.3 6 V
Feedback voltage VFB –0.3 6 V
Output voltage VOUT –0.3 VIN + 0.3 V
Maximum output current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation PDISS See Thermal Information
Temperature Operating junction, TJ –40 150 °C
Storage, Tstg –55 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage VOUT + VDO (VIN) VOUT + 0.3 5.5 V
VEN Enable supply voltage 0 VIN 5.5 V
VBIAS(1) BIAS supply voltage VOUT + VDO (VBIAS)(2) VOUT + 1.6(2) 5.5 V
VOUT Output voltage 0.8 3.3 V
IOUT Output current 0 1.5 A
COUT Output capacitor 2.2 µF
CIN Input capacitor(3) 1 µF
CBIAS Bias capacitor 0.1 1 µF
TJ Operating junction temperature –40 125 °C
BIAS supply is required when VIN is below VOUT + 1.62 V.
VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.

Thermal Information

THERMAL METRIC(1) TPS748(2) UNIT
RGW (VQFN) DRC (VSON)
20 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance(3) 35.6 44.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(4) 33.3 50.3 °C/W
RθJB Junction-to-board thermal resistance(5) 15 19.6 °C/W
ψJT Junction-to-top characterization parameter(6) 0.4 0.7 °C/W
ψJB Junction-to-board characterization parameter(7) 15.2 17.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(8) 3.8 4.3 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
  1. i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.                         
    . ii. DRC: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.                    
  2. i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.                         
    . ii. DRC: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
  3. These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Estimating Junction Temperature section of this data sheet.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Electrical Characteristics

At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS BIAS pin voltage range 2.7 5.5 V
VREF Internal reference (Adj.) TJ = 25°C 0.796 0.8 0.804 V
VOUT(ΔVIN) Output voltage range VIN = 5 V, IOUT = 1.5 A VREF 3.6 V
Accuracy(1) 2.97 V ≤ VBIAS ≤ 5.5 V,
50 mA ≤ IOUT ≤ 1.5 A
–2% ±0.5% 2%
VOUT(ΔIOUT) Line regulation VOUT(nom) + 0.3 ≤ VIN  ≤ 5.5 V 0.03 %/V
VOUT Load regulation 50 mA ≤ IOUT ≤ 1.5 A 0.09 %/A
VDO VIN dropout voltage(2) IOUT = 1.5 A,
VBIAS – VOUT(nom) ≥ 3.25 V(3)
60 165 mV
VBIAS dropout voltage(2) IOUT = 1.5 A, VIN = VBIAS 1.31 1.6 V
ICL Current limit VOUT = 80% × VOUT(nom) 2 5.5 A
IBIAS BIAS pin current 1 2 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V 1 50 μA
IFB Feedback pin current –1 0.150 1 μA
PSRR Power-supply rejection
(VIN to VOUT)
1 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
60 dB
300 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
30
Power-supply rejection
(VBIAS to VOUT)
1 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
50 dB
300 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
30
Vn Output noise voltage 100 Hz to 100 kHz,
IOUT = 1.5 A, CSS = 1 nF
25 × VOUT μVRMS
tSTR Minimum startup time RLOAD for IOUT = 1.0 A, CSS = open 200 μs
ISS Soft-start charging current VSS = 0.4 V 440 nA
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 50 mV
VEN(dg) Enable pin deglitch time 20 μs
IEN Enable pin current VEN = 5 V 0.1 1 μA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.3 V
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT 0.1 1 μA
TJ Operating junction temperature –40 125 °C
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 °C
Reset, temperature decreasing 140
Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.

Typical Characteristics IOUT = 50 mA

At TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted.
TPS748 tc_vin_reg_bvs074.gif
Figure 1. VIN Line Regulation
TPS748 tc_load_reg_ma_bvs074.gif
Figure 3. Load Regulation
TPS748 tc_vdo-io_tmp_bvs074.gif
Figure 5. VIN Dropout Voltage vs IOUT and Temperature (TJ)
TPS748 tc_vi_drop-vb_bvs074.gif
Figure 7. VIN Dropout Voltage vs (VBIAS – VOUT) and Temperature (TJ)
TPS748 tc_vbias-frq_bvs074.gif
Figure 9. VBIAS PSRR vs Frequency
TPS748 tc_psrr-vivo_bvs074.gif
Figure 11. VIN PSRR vs (VIN – VOUT)
TPS748 tc_bias-io_tmp_bvs074.gif
Figure 13. BIAS Pin Current vs Output Current and Temperature (TJ)
TPS748 tc_iss-tmp_tj_bvs074.gif
Figure 15. Soft-Start Charging Current (ISS) vs
Temperature (TJ)
TPS748 tc_cur-vbias_vo_bvs074.gif
Figure 17. Current Limit vs (VBIAS – VOUT)
TPS748 tc_vbias_reg_bvs074.gif
Figure 2. VBIAS Line Regulation
TPS748 tc_load_reg_bvs074.gif
Figure 4. Load Regulation at Light Load
TPS748 tc_vi_drop-vb_tj_bvs074.gif
Figure 6. VIN Dropout Voltage vs (VBIAS – VOUT) and Temperature (TJ)
TPS748 tc_vb_vdo-io_tmp_tj_bvs074.gif
Figure 8. VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS748 tc_vin-frq_bvs074.gif
Figure 10. VIN PSRR vs Frequency
TPS748 tc_noise_dens_bvs074.gif
Figure 12. Noise Spectral Density
TPS748 tc_bias-vb_tmp_bvs074.gif
Figure 14. BIAS Pin Current vs VBIAS and Temperature (TJ)
TPS748 tc_lopg-pg_cur_bvs074.gif
Figure 16. Low-Level PG Voltage vs Current

Typical Characteristics IOUT = 1 A

At TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted.
TPS748 tc_vbias-trans_bvs074.gif
Figure 18. VBIAS Line Transient
TPS748 tc_out_load_trans_bvs074.gif
Figure 20. Output Load Transient Response
TPS748 tc_pwr_up_dwn_bvs074.gif
Figure 22. Power-Up/Power-Down
TPS748 tc_vin-trans_bvs074.gif
Figure 19. VIN Line Transient
TPS748 tc_turn_on_bvs074.gif
Figure 21. Turnon Response