SGLS247C September   2011  – December 2025 TPS763-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Output Pulldown
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Device Feedback Resistors
      2. 7.1.2 Recommended Capacitor Types
        1. 7.1.2.1 Recommended Capacitors (Legacy Chip)
        2. 7.1.2.2 Recommended Capacitors (New Chip)
      3. 7.1.3 Input and Output Capacitor Requirements
        1. 7.1.3.1 Input Capacitor Requirements
        2. 7.1.3.2 Output Capacitor Requirements
      4. 7.1.4 Reverse Current
      5. 7.1.5 Feed-Forward Capacitor (CFF)
      6. 7.1.6 Power Dissipation (PD)
      7. 7.1.7 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Programming
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Power Dissipation and Junction Temperature
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Device Nomenclature
      2. 8.2.2 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Specified at TJ = –40°C to 125°C, VIN = VOUT(nom) + 1.0V or VIN = 2.7V (whichever is greater), IOUT = 1mA, EN = VIN, CIN = 1.0µF, COUT = 4.7µF (unless otherwise noted). Typical values are at TJ= 25ºC.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output voltage TPS76301-Q1 (for legacy chip) 3.25V > VIN ≥ 2.7V, 2.5V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 75mA, TJ = 25°C 0.98 × VOUT VOUT 1.02 × VOUT V
3.25V > VIN ≥ 2.7V, 2.5V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 75mA 0.97 × VOUT VOUT 1.03 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 100mA, TJ = 25°C 0.98 × VOUT 1.02 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 100mA 0.97 × VOUT 1.03 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 150mA, TJ = 25°C 0.975 × VOUT 1.025 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 150mA 0.9625 × VOUT 1.0375 × VOUT
TPS76301-Q1 (for new chip) 3.25V > VIN ≥ 2.7V, 2.5V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 75mA, TJ = 25°C 0.985 × VOUT VOUT 1.015 × VOUT
3.25V > VIN ≥ 2.7V, 2.5V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 75mA 0.98 × VOUT VOUT 1.02 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 100mA, TJ = 25°C 0.985 × VOUT 1.015 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 100mA 0.98 × VOUT 1.02 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 150mA, TJ = 25°C 0.985 × VOUT 1.015 × VOUT
VIN ≥ 3.25V, 5.0V ≥ VOUT ≥ 1.5V, IOUT = 1mA to 150mA 0.98 × VOUT 1.02 × VOUT
TPS76316-Q1 (for legacy chip) VIN = 2.7V, IOUT = 1mA to 75mA, TJ = 25°C 1.568 1.6 1.632
VIN = 2.7V, IOUT = 1mA to 75mA 1.552 1.6 1.648
VIN = 3.25V, IOUT = 1mA to 100mA, TJ = 25°C 1.568 1.6 1.632
VIN = 3.25V, IOUT = 1mA to 100mA 1.552 1.6 1.648
VIN = 3.25V, IOUT = 1mA to 150mA, TJ = 25°C 1.56 1.6 1.64
VIN = 3.25V, IOUT = 1mA to 150mA 1.536 1.6 1.664
TPS76318-Q1 (for legacy chip) VIN = 2.7V, IOUT = 1mA to 75mA, TJ = 25°C 1.764 1.8 1.836
VIN = 2.7V, IOUT = 1mA to 75mA 1.746 1.8 1.854
VIN = 3.25V, IOUT = 1mA to 100mA, TJ = 25°C 1.764 1.8 1.836
VIN = 3.25V, IOUT = 1mA to 100mA 1.746 1.8 1.854
VIN = 3.25V, IOUT = 1mA to 150mA, TJ = 25°C 1.755 1.8 1.845
VIN = 3.25V, IOUT = 1mA to 150mA 1.733 1.8 1.867
VOUT Output voltage TPS76325-Q1 (for legacy chip) IOUT = 1mA to 100mA, TJ = 25°C 2.45 2.5 2.55 V
IOUT = 1mA to 100mA 2.425 2.5 2.575
IOUT = 1mA to 150mA, TJ = 25°C 2.438 2.5 2.562
IOUT = 1mA to 150mA 2.407 2.5 2.593
TPS76330-Q1 (for legacy chip) IOUT = 1mA to 100mA, TJ = 25°C 2.94 3 3.06
IOUT = 1mA to 100mA 2.91 3 3.09
IOUT = 1mA to 150mA, TJ = 25°C 2.925 3 3.075
IOUT = 1mA to 150mA 2.888 3 3.112
TPS76333-Q1 (for legacy chip) IOUT = 1mA to 100mA, TJ = 25°C 3.234 3.3 3.366
IOUT = 1mA to 100mA 3.201 3.3 3.399
IOUT = 1mA to 150mA, TJ = 25°C 3.218 3.3 3.382
IOUT = 1mA to 150mA 3.177 3.3 3.423
TPS76333-Q1 (for new chip) IOUT = 1mA to 100mA, TJ = 25°C 3.234 3.3 3.366
IOUT = 1mA to 100mA 3.20925 3.3 3.39075
IOUT = 1mA to 150mA, TJ = 25°C 3.234 3.3 3.366
IOUT = 1mA to 150mA 3.20925 3.3 3.39075
TPS76350-Q1 (for legacy chip) IOUT = 1mA to 100mA, TJ = 25°C 4.875 5 5.125
IOUT = 1mA to 100mA 4.825 5 5.175
IOUT = 1mA to 150mA, TJ = 25°C 4.85 5 5.15
IOUT = 1mA to 150mA 4.8 5 5.2
TPS76350-Q1 (for new chip) IOUT = 1mA to 100mA, TJ = 25°C 4.9 5 5.1
IOUT = 1mA to 100mA 4.8625 5 5.1375
IOUT = 1mA to 150mA, TJ = 25°C 4.9 5 5.1
IOUT = 1mA to 150mA 4.8625 5 5.1375
IQ Quiescent current (GND current) For legacy chip IOUT = 1mA to 150mA, TJ = 25°C 85 100 µA
IOUT = 1mA to 150mA 140
For new chip IOUT = 0mA 65 125
IOUT = 1mA to 150mA, TJ = 25°C 765 890
IOUT = 1mA to 150mA 1120
ΔVOUT(ΔVOUT) Output voltage line regulation (ΔVOUT/VOUT) For legacy chip VOUT(NOM) +1.0V ≤ VIN ≤ 10V, VIN  ≥ 3.5V, TJ = 25°C 0.04 0.07 %/V
VOUT(NOM) +1.0V ≤ VIN ≤ 10V, VIN  ≥ 3.5V 0.1
For new chip VOUT(NOM) +1.0V ≤ VIN ≤ 10V, VIN  ≥ 3.5V, TJ = 25°C 0.01
VOUT(NOM) +1.0V ≤ VIN ≤ 10V, VIN  ≥ 3.5V 0.01
Vn Output noise voltage For legacy chip BW = 300Hz to 50kHz, VOUT = 3.3V , COUT = 10µF 140 µVRMS
For new chip BW = 300Hz to 50kHz, VOUT = 3.3V , COUT = 4.7µF 165
ICL Output current limit For legacy chip VOUT = 0V 0.5 0.8 1.5 A
For new chip 0.8 1.05
ISTANDBY Standby current For legacy chip EN < 0.5V, TJ = 25℃ 0.5 1 µA
EN < 0.5V 2
For new chip EN < 0.15V, TJ = 25℃ 1.25
EN < 0.15V 1.12 3.75
EN High level enable input voltage For legacy chip 1.4 2 V
Low level enable input voltage 0.5 1.2
High level enable input voltage For new chip 0.85 1.6
Low level enable input voltage 0.15 0.72
PSRR Power-supply ripple rejection For legacy chip COUT = 10µF, f = 1kHz, TJ = 25 ℃ 60 dB
For new chip COUT = 4.7µF, f = 1kHz, TJ = 25 ℃ 58
IEN Input current (EN) For legacy chip EN = 0V –0.01 –0.5 µA
EN = VIN –0.01 –0.5
For new chip EN = 0V –0.35 –0.7
EN = VIN 0.008 0.8
VDO Dropout voltage TPS76325-Q1 (for legacy chip) IOUT = 0mA, TJ = 25℃ 0.2 mV
IOUT = 1mA, TJ = 25℃ 3
IOUT = 50mA, TJ = 25℃ 120 150
IOUT = 50mA 200
IOUT = 75mA, TJ = 25℃ 180 225
IOUT = 75mA 300
IOUT = 100mA, TJ = 25℃ 240 300
IOUT = 100mA 400
IOUT = 150mA, TJ = 25℃ 360 450
IOUT = 150mA 600
TPS76333-Q1 (for legacy chip) IOUT = 0mA, TJ = 25℃ 0.2
IOUT = 1mA, TJ = 25℃ 3
IOUT = 50mA, TJ = 25℃ 100 125
IOUT = 50mA 166
IOUT = 75mA, TJ = 25℃ 150 188
IOUT = 75mA 250
IOUT = 100mA, TJ = 25℃ 200 250
IOUT = 100mA 333
IOUT = 150mA, TJ = 25℃ 300 375
IOUT = 150mA 500
VDO Dropout voltage TPS76350-Q1 (for legacy chip) IOUT = 0mA, TJ = 25℃ 0.2 mV
IOUT = 1mA, TJ = 25℃ 2
IOUT = 50mA, TJ = 25℃ 60 75
IOUT = 50mA 100
IOUT = 75mA, TJ = 25℃ 90 113
IOUT = 75mA 150
IOUT = 100mA, TJ = 25℃ 120 150
IOUT = 100mA 200
IOUT = 150mA, TJ = 25℃ 180 225
IOUT = 150mA 300
TPS763xx-Q1 (for new chip) IOUT = 0mA, TJ = 25℃ 1
IOUT = 1mA, TJ = 25℃ 10.5
IOUT = 50mA, TJ = 25℃ 125 150
IOUT = 50mA 205
IOUT = 75mA, TJ = 25℃ 135 155
IOUT = 75mA 210
IOUT = 100mA, TJ = 25℃ 145 165
IOUT = 100mA 225
IOUT = 150mA, TJ = 25℃ 175 195
IOUT = 150mA 260