6.4 Thermal Informationover operating free-air temperature range (unless otherwise noted)
||Junction-to-ambient thermal resistance
||Junction-to-case (top) thermal resistance
||Junction-to-board thermal resistance
||Junction-to-top characterization parameter
||Junction-to-board characterization parameter
||Junction-to-case (bottom) thermal resistance
Thermal data for the DRB and DCQ packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
- i. DRB: The exposed pad is connected to the PCB ground layer through a 2-mm x 2-mm thermal via array.
.ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3-mm x 2-mm thermal via array.
- i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
.ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
- These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see Thermal Considerations and Estimating Junction Temperature of this data sheet.