SLVS351Q September   2002  – June 2025 TPS796

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Active Discharge (New Chip)
      2. 6.3.2 Shutdown
      3. 6.3.3 Start-Up
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Regulator Protection
        1. 6.3.5.1 Current Limit
        2. 6.3.5.2 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Feed-forward Capacitor (CFF)
      4. 7.1.4 Adjustable Configuration
      5. 7.1.5 Load Transient Response
      6. 7.1.6 Dropout Voltage
        1. 7.1.6.1 Exiting Dropout
      7. 7.1.7 Noise Reduction Pin (legacy chip)
      8. 7.1.8 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Best Design Practices
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
        2. 7.4.1.2 Regulator Mounting
        3. 7.4.1.3 Estimating Junction Temperature
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at operating temperature range (TJ = –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, and COUT = 10µF and CNR = 0.01µF(Legacy Chip only), unless otherwise noted. All typical values at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input Voltage  Legacy chip 2.7 5.5 V
New chip 2.7 6.0
VFB Internal reference (TPS79601) 1.2 1.225 1.25 V
IOUT Continuous output current 0 1 A
VOUT Output voltage range (TPS79601) 1.225 5.5-VDO V
VOUT Output accuracy TPS79601 0 µA ≤ IOUT ≤ 1 A,
VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)		 0.98 VOUT(nom) 1.02 VOUT(nom) %
VOUT Output accuracy Fixed VOUT < 5V 0 µA ≤ IOUT ≤ 1 A,
VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)		 -2.0 2.0 %
VOUT Output accuracy Fixed VOUT = 5V 0 µA ≤ IOUT ≤ 1 A,
VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)		 -3.0 3.0 %
ΔVOUT/ΔVIN Line regulation VOUT + 1 V ≤ VIN ≤ 5.5 V 0.05 0.12 %/V
ΔVOUT/ΔIOUT Load regulation 0 µA ≤ IOUT ≤ 1 A 5 mV
VDO Dropout voltage TPS79628 VIN= VOUT - 0.1V  IOUT = 1A 270 365 mV
Dropout voltage TPS79628DRB IOUT = 250mA 52 90
Dropout voltage TPS79630 IOUT = 1 A 250 345
Dropout voltage TPS79633 IOUT = 1 A 220 325
Dropout voltage TPS79650 IOUT = 1 A 220 300
ICL Output current limit VOUT = 0 (legacy chip) 2.4 4.2 A
ICL Output current limit VIN = VOUT(nom) + 1.25 V or 2.0 V (whichever is greater), VOUT = 0.9 x VOUT(nom) (new chip only) (2) 1.04 1.65 A
ISC Short-circuit current limit VOUT = 0 (new chip only) 550 mA
IGND Ground current 0µA ≤ IOUT ≤ 1A (legacy chip) 265 385 µA
IGND Ground current 0µA ≤ IOUT ≤ 1A (new chip) 700 1100 µA
ISHDN Shutdown current VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V 0.07 1 µA
IFB Feedback pin current VFB = 1.225 V 1 µA
PSRR Power-supply rejection ratio f = 100 Hz, IOUT = 10mA (legacy chip) 59 dB
f = 100 Hz, IOUT = 10mA (new chip) 64
f = 100 Hz, IOUT = 1A (legacy chip) 54
f = 100 Hz, IOUT = 1A (new chip) 74
f = 10 kHz, IOUT = 1A (legacy chip) 53
f = 10 kHz, IOUT = 1A (new chip) 49
f = 100 kHz, IOUT = 1A (legacy chip) 42
f = 100 kHz, IOUT = 1A (new chip) 42
Vn Output noise voltage BW = 100Hz to 100kHz, IOUT = 1A CNR = 0.001 µF 54 µVRMS
CNR = 0.0047 µF 46
CNR = 0.01 µF 41
CNR = 0.1 µF 40
BW = 10Hz to 100kHz, IOUT = 1A new chip (10 78 µVRMS
tstr Time, start-up  RL = 3Ω, COUT = 1 µF CNR = 0.001 µF 50 µs
RL = 3Ω, COUT = 1 µF CNR = 0.0047 µF 75
RL = 3Ω, COUT = 1 µF CNR = 0.01 µF 110
tstr Time, start-up  RL = 3Ω, COUT = 1 µF new chip 550 µs
IEN Enable pin current VEN = 0 V -1 1 µA
RPULLDOWN Pulldown resistance VIN = 3.3V (new chip only) 100 Ω
VUVLO UVLO threshold VIN rising (legacy chip) 2.25 2.65 V
VIN rising (new chip) 1.28 1.62
VUVLO(HYST) UVLO hysteresis VIN hysteresis (legacy chip) 100 mV
VIN hysteresis (new Chip) 130
VEN(HI) High-level enable input voltage 2.7V(1) ≤ VIN ≤ 5.5V (legacy chip) 1.7 VIN V
2.7V(1) ≤ VIN ≤ 5.5V (new chip) 0.85 VIN
VEN(LOW) Low-level enable input voltage 2.7V(1) ≤ VIN ≤ 5.5V (legacy chip) 0.7
2.7V(1) ≤ VIN ≤ 5.5V (new chip) 0.425
TSD Thermal shutdown temperature Shutdown, temperature increasing legacy chip 165 ℃
TSD Thermal shutdown temperature Shutdown, temperature increasing new chip 170
℃
TSD Thermal shutdown temperature Reset, temperature decreasing legacy chip 140
℃
TSD Thermal shutdown temperature Reset, temperature decreasing new chip 155
℃
(1) Minimum VIN = VOUT +1V or 2.7V, whichever is greater. VOUT(NOM) =5V is tested at  VIN (NOM) = 5.5 V
(2) VOUT(NOM) =5V is tested at  VIN (NOM) = VOUT(NOM) +1V