SBVS399A December 2021 – May 2022 TPS7A13
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.
Equation 2 calculates the maximum allowable power dissipation for the device in a given package:
Equation 3 represents the actual power being dissipated in the device:
If the load current is much greater than I_{GND(IN)} and I_{GND(BIAS)}, Equation 3 can be simplified as:
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS7A13 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air.
The maximum power dissipation determines the maximum allowable junction temperature (T_{J}) for the device. According to Equation 5, maximum power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R_{θJA}) of the combined PCB and device package and the temperature of the ambient air (T_{A}). The equation is rearranged in Equation 6 for output current.
Unfortunately, this thermal resistance (R_{θJA}) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The R_{θJA} recorded in the Section 6.4 table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, R_{θJA} is actually the sum of the YCK package junction-to-case (bottom) thermal resistance (R_{θJC(bot)}) plus the thermal resistance contribution by the PCB copper.