The device is designed to be stable using low equivalent series resistance (ESR) and low equivalent series inductance (ESL) ceramic capacitors at the input, output, and noise-reduction pin. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature. The use of Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature. Make sure to derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for a capacitance derating of approximately 50%, but at high V_IN and V_OUT conditions (V_IN = 5.5 V to V_OUT = 5.0 V) and temperature extremes, the derating can be greater than 50%, and must be taken into consideration.

The device requires input, output, and noise-reduction capacitors for proper operation of the LDO. Use the nominal or larger than nominal input and output capacitors as specified in the Section 6.3 table. Place input and output capacitors as close as possible to the corresponding pin and make the capacitor GND connections are as close as possible to the device GND pin to shorten transient currents on the return path. Using a larger input capacitor or a bank of capacitors with various values is always good design practice to counteract input trace inductance, improve transient response, and reduce input ripple and noise. Similarly, multiple capacitors on the output reduce charge pump ripple and optimize PSRR; see the Section 8.1.7 section.

Use the nominal noise-reduction C_NR/SS capacitor because using a larger C_NRSS capacitor can lengthen the start-up time as mentioned previously.