SBVS343A March   2019  – September 2019 TPS7A78

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Schematic Half-Bridge Configuration
      2.      Typical Schematic Full-Bridge Configuration
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active Bridge Control
      2. 7.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 7.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 7.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 7.3.5 Dropout Voltage Regulation
      6. 7.3.6 Current Limit
      7. 7.3.7 Programmable Power-Fail Detection
      8. 7.3.8 Power-Good (PG) Detection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitors Requirements
      3. 8.1.3 Startup Behavior
      4. 8.1.4 Load Transient
      5. 8.1.5 Standby Power and Output Efficiency
      6. 8.1.6 Reverse Current
      7. 8.1.7 Switched-Capacitor Stage Output Impedance
      8. 8.1.8 Power Dissipation (PD)
      9. 8.1.9 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating the Cap-Drop Capacitor CS
          1. 8.2.2.1.1 CS Calculations for the Typical Design
        2. 8.2.2.2 Calculating the Surge Resistor RS
          1. 8.2.2.2.1 RS Calculations for the Typical Design
        3. 8.2.2.3 Checking for the Device Maximum ISHUNT Current
          1. 8.2.2.3.1 ISHUNT Calculations for the Typical Design
        4. 8.2.2.4 Calculating the Bulk Capacitor CSCIN
          1. 8.2.2.4.1 CSCIN Calculations for the Typical Design
        5. 8.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. 8.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design
        6. 8.2.2.6 Summary of the Typical Application Design Components
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
        2. 11.1.1.2 SIMPLIS Model
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VAC(2) Connected via CS(3) and RS(3)(4) on either AC+ or AC– 18(5) VRMS
fAC Line frequency 50 20,000 Hz
ISURGE Peak transient current into or out of either the AC+ or AC– pins (during hot plug for ≤ 100 µs) 2.5 A
ISHUNT AC current during shunt event on either AC+ or AC- pins 200 mARMS
VSCIN DC supply mode, voltage applied to the SCIN pin for devices with VLDO_OUT ≤ 3.4 V 17(6) 23 V
CSCIN Bulk capacitor for VAC supply mode 22 µF
CSCIN Bulk capacitor for DC-supply mode 1.0
CSC1 Switched-capacitor stage 1 1 4.7(7) µF
CSC2 Switched-capacitor stage 2 1 4.7(7) µF
CLDO_IN LDO_IN  capacitor 0.68 10 1000 µF
CLDO_OUT LDO_OUT capacitor 0.68 1 100 µF
R1 PFD top resistor divider 0 200 kΩ
R3 & R4 Power-good and power-fail  pullup resistors 10 100 kΩ
IOUT Output current 0 120 mA
TJ Operating junction temperature –40 125 ℃
(1) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB) Configurations section for details.
(2) Theoretically there is no upper limit to the VAC supply voltage because this voltage is dropped across the CS capacitor; see the Calculating the Cap-Drop Capacitor section for details.
(3) The voltage ratings for the cap-drop capacitor CS and the surge resistor RS must be able to handle the peak VAC supply voltage; see the Typical Application section for details.
(4) The surge resistor RS is required to limit the inrush current into or out off either AC+ or AC– pins during hot-plug or surge current events; see the Calculating the Surge Resistor section for details. 
(5) Only available for devices with ≤ 3.3-V output voltage options.
(6) DC-supply mode is also availabe for 3.6-V devices but with a minmum required VSCIN supply voltage of 18 V. 
(7) A 16 V or higher voltage rating is recommended for the CSC1 capacitor, and a 10 V or higher voltage rating is recommeded for the CSC2 capacitor.