SBVS304A June 2017 – November 2017 TPS7A83A
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Successfully implementing an LDO in an application depends on the application requirements. This section discusses key device features and how to best implement them to achieve a reliable design.
The TPS7A83A can be used either with the internal ANY-OUT network or by using external resistors. Using the ANY-OUT network allows the TPS7A83A to be programmed from 0.8 V to 3.95 V. For an output voltage range greater than 3.95 V and up to 5.2 V, external resistors must be used. This configuration is referred to as the adjustable configuration of the TPS7A83A throughout this document. Figure 47 shows that the output voltage is set by two resistors. 0.75% accuracy can be achieved with an external BIAS for VIN lower than 2.2 V.
Use Equation 1 to calculate R1 and R2 for any output voltage range. This resistive network must provide a current equal to or greater than 5 μA for dc accuracy. TI recommends using an R1 of approximately 12 kΩ to optimize the noise and PSRR.
Table 4 shows the resistor combinations required to achieve several common rails using standard 1%-tolerance resistors.
|NOMINAL OUTPUT VOLTAGE
|FEEDBACK RESISTOR VALUES||CALCULATED OUTPUT VOLTAGE
|R1 (kΩ)||R2 (kΩ)|
The TPS7A83A can use either external resistors or the internally-matched ANY-OUT feedback resistor network to set output voltage. The ANY-OUT resistors are accessible via pin 2 and pins 5 to 11 and are used to program the regulated output voltage. Each pin is can be connected to ground (active) or left open (floating), or connected to SNS. ANY-OUT programming is set by Equation 2 as the sum of the internal reference voltage (VNR/SS = 0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 5 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open or floating, the output is thereby programmed to the minimum possible output voltage equal to VFB.
|ANY-OUT PROGRAM PINS (Active Low)||ADDITIVE OUTPUT VOLTAGE LEVEL|
|Pin 5 (50mV)||50 mV|
|Pin 6 (100mV)||100 mV|
|Pin 7 (200mV)||200 mV|
|Pin 9 (400mV)||400 mV|
|Pin 10 (800mV)||800 mV|
|Pin 11 (1.6V)||1.6 V|
Table 6 provides a full list of target output voltages and corresponding pin settings when the ANY-OUT pins are only tied to ground or left floating. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There are several alternative ways to set the output voltage. The program pins can be driven using external general-purpose input/output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the output voltage is set according to Equation 3 except that R1 and R2 are internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by lowering the value of R1; see the Increasing ANY-OUT Resolution for LILO Conditions section for additional information.
For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable Operation section).
|50 mV||100 mV||200 mV||400 mV||800 mV||1.6 V||VOUT(NOM)
|50 mV||100 mV||200 mV||400mV||800mV||1.6V|
Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ, see the section) the output voltage is set as shown in Figure 48 by grounding the appropriate control pins. When grounded, all control pins add a specific voltage on top of the internal reference voltage (VNR/SS = 0.8 V). Use Equation 4 and Equation 5 to calculate the output voltage. Figure 48 and Figure 49 show a 0.9-V output voltage, respectively, that provides an example of the circuit usage with and without BIAS voltage.
As with the adjustable operation, the output voltage is set according to Equation 3, except that R1 and R2 are internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by lowering the value of R1. One of the more useful pin combinations is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. Table 7 lists the new additive output voltage levels.
|ANY-OUT PROGRAM PINS (Active Low)||ADDITIVE OUTPUT VOLTAGE LEVEL|
|Pin 5 (50mV)||25 mV|
|Pin 6 (100mV)||50 mV|
|Pin 7 (200mV)||100 mV|
|Pin 9 (400mV)||200 mV|
|Pin 11 (1.6V)||800 mV|
The TPS7A83A is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input, output, and noise-reduction pin (NR/SS). Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature; derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for a capacitance derating of approximately 50%, but at high VIN and VOUT conditions (for example, VIN = 5.6 V to VOUT = 5.2 V) the derating can be greater than 50% and must be taken into consideration.
The TPS7A83A is designed and characterized for operation with ceramic capacitors of 22 µF or greater (10 μF or greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. Using at least a 22-µF capacitor is highly recommended at the input to minimize input impedance. Place the input and output capacitors as near as practical to the respective input and output pins to minimize trace parasitic. If the trace inductance from the input supply to the TPS7A83A is high, a fast current transient can cause VIN to ring above the absolute maximum voltage rating and damage the device. This situation can be mitigated by additional input capacitors to dampen the ringing and to keep the ringing below the device absolute maximum ratings.
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a
10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher capacitance CFF can be used; however, the start-up time is longer, and the PG signal can incorrectly indicate that the output voltage is settled. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator.
The TPS7A83A features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CNR/SS).The use of an external CNR/SS is highly recommended, especially to minimize in-rush current into the output capacitors. This soft-start eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces peak in-rush current during start-up, minimizing start-up transients to the input power bus.
To achieve a monotonic start-up, the TPS7A83A error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Use Equation 6 to calculate the soft-start ramp time:
INR/SS is provided in the table.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the device noise floor. The LPF is a single-pole filter and Equation 7 to calculates the cutoff frequency. The typical value of RNR/SS is 250 kΩ. Increasing the CNR/SS capacitor has a greater affect because the output voltage increases when the noise from the reference is gained up even more at higher output voltages. For low-noise applications, a 10-nF to 1-µF CNR/SS is recommended. When a CNR/SS capacitor gets larger, the capacitor leakage increases, causing a longer than expected start-up time.
The output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CNR/SS). This soft-start eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, thus minimizing start-up transients to the input power bus.
The output voltage (VOUT) rises proportionally to VNR/SSduring start-up as the LDO regulates so that the feedback voltage equals the NR/SS voltage (VFB = VNR/SS). As such, the time required for VNR/SS to reach its nominal value determines the rise time of VOUT (start-up time).
Not using a noise-reduction capacitor on the NR/SS pin can result in output voltage overshoot of approximately 10%. Using a capacitor on the NR/SS pin minimizes the overshoot.
Values for the soft-start charging currents are provided in the Specifications table.
Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, Equation 8 can estimate this soft-start current:
The UVLO circuits ensure that the device stays disabled before the input or bias supplies reach the minimum operational voltage range, and ensures that the device properly shuts down when either the input or BIAS supply collapses.
|A||Turnon, VIN ≥ VUVLO_1,2(IN), and VBIAS ≥ VUVLO(BIAS)||Off||Start-up|
|B||Regulation||On||Regulates to target VOUT|
|C||Brownout, VIN ≥ VUVLO_1,2(IN) – VHYS_1,2(IN)
or VBIAS ≥ VUVLO(BIAS) – VHYS(BIAS)
|On||The output can fall out of regulation but the device is still enabled|
|D||Regulation||On||Regulates to target VOUT|
|E||Brownout, VIN < VUVLO_1,2(IN) – VHYS_1,2(IN)
or VBIAS ≥ VUVLO(BIAS) – VHYS(BIAS)
|Off||The device is disabled and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLO fault is removed when either the IN or BIAS UVLO rising threshold is reached by the input or bias voltage and a normal start-up then follows.|
|F||Regulation||On||Regulates to target VOUT|
|G||Turnoff, VIN < VUVLO_1,2(IN) – VHYS_1,2(IN)
or VBIAS < VUVLO(BIAS) – VHYS(BIAS)
|Off||The output falls because of the load and active discharge circuit|
Similar to many other LDOs with this feature, the UVLO circuits take a few microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the UVLO circuits do not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLO circuits are not given enough time to fully discharge the internal nodes, the outputs are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall time of the input supply when operating near the minimum VIN.
The PG circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The PG circuit asserts whenever FB, VIN, or EN are below their thresholds. Figure 51 and Table 9 describe the PG operation versus the output voltage.
|REGION||EVENT||PG STATUS||FB VOLTAGE|
|A||Turnon||0||VFB < VIT(PG) + VHYS(PG)|
|B||Regulation||Hi-Z||VFB ≥ VIT(PG)|
|C||Output voltage dip||Hi-Z|
|E||Output voltage dip||0||VFB < VIT(PG)|
|F||Regulation||Hi-Z||VFB ≥ VIT(PG)|
|G||Turnoff||0||VFB < VIT(PG)|
The PG pin is open-drain, and connecting a pullup resistor to an external supply enables others devices to receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices.
To ensure proper operation of the PG circuit, the pullup resistor value must be from 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the PG transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the PG node. If the pullup resistor is outside of this range, then the PG signal may not read a valid digital logic level.
Using a large CFF with a small CNR/SS causes the PG signal to incorrectly indicate that the output voltage has settled during turnon. The CFF time constant must be greater than the soft-start time constant to ensure proper operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator.
The state of PG is only valid when the device operates above the minimum supply voltage. During short brownout events and at light loads, PG does not assert because the output voltage (therefore VFB) is sustained by the output capacitance.
LDO ac performance includes power-supply rejection ratio, output-current transient response, and output noise. These metrics are primarily a function of open-loop gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The output noise is primarily a result of the reference and error amplifier noise.
PSRR is a measure of how well the LDO control loop rejects signals from VIN to VOUT across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 9 gives the PSRR calculation as a function of frequency for the input signal [VIN(f)] and output signal [VOUT(f)].
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.
Figure 52 shows a simplified diagram of PSRR versus frequency.
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for the TPS7A83A.
The TPS7A83A features an innovative circuit to boost the PSRR from 200 kHz to 1 MHz; see Figure 1. To achieve the maximum benefit of this PSRR boost circuit, TI recommends using a capacitor with a minimum impedance in the 100-kHz to 1-MHz band.
The TPS7A83A is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A83A can be used in a phase-locked loop (PLL)-based clocking circuit and can be used for minimum phase noise, or in test and measurement systems where even small power-supply noise fluctuations reduce system dynamic range.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 53 shows a simplified output voltage noise density plot versus frequency.
For further details, see the How to Measure LDO Noise white paper.
Table 10 describes several ways how the ultra-low noise floor and PSRR of the device can be improved.
|CNR/SS||+++||No effect||No effect||+++||+||No effect|
|COUT||No effect||+||+++||No effect||+||+++|
|VIN – VOUT||+||+||+||+++||+++||++|
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the output voltage noise floor. The LPF is a single-pole filter, and Equation 10 calculates the cutoff frequency. The typical value of RNR/SS is 250 kΩ. The effect of the CNR/SS capacitor increases when VOUT(nom) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, TI recommends a 10-nF to 1-µF CNR/SS.
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR.
A larger COUT or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high-power dissipation across the die increases the output noise because of the increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and isolating VOUT at high frequencies.
Table 11 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions with an input voltage of 5.5 V and a load current of 2 A. The 5-V output was chosen as a worst-case nominal operation for output voltage noise.
|OUTPUT VOLTAGE NOISE (µVRMS)||CNR/SS (nF)||CFF (nF)||COUT (µF)|
Figure 54 shows that the device internal charge pump generates a minimal amount of noise.
Using a BIAS rail minimizes the internal charge-pump noise when the internal voltage is clamped, thereby reducing the overall output noise floor.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 55 and described in Table 12 are broken down in this section. Regions A, E, and H are where the output voltage is in steady-state.
|B||Output current ramping||Initial voltage dip is a result of the depletion of the output capacitor charge|
|C||LDO responding to transient||Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation|
|D||Reaching thermal equilibrium||At high load currents the LDO takes some time to heat up. During this time the output voltage changes slightly.|
|F||Output current ramping||Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase|
|G||LDO responding to transient||Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor|
The transient response peaks (VOUT(max) and VOUT(min)) are improved by using more output capacitance; however, doing so slows down the recovery time (Wrise and Wfall). Figure 56 shows these parameters during a load transient, with a given pulse duration (PW) and current levels (IOUT(LO) and IOUT(HI)).
The device features an output voltage accuracy of 0.75% maximum, with BIAS, that includes the errors introduced by the internal reference, load regulation, line regulation, and operating temperature as specified by the table. Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent.
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and output voltage (VDO = VIN – VOUT) that is required for regulation. When VIN drops below the required VDO for the given load current, the device functions as a resistive switch and does not regulate output voltage. Figure 57 shows that dropout voltage is proportional to the output current because the device is operating as a resistive switch.
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect to VIN on this device because of the internal charge pump. Dropout voltage increases exponentially when the input voltage nears its maximum operating voltage.
Some applications can have transients that place the LDO into dropout, such as slower ramps on VIN for start-up or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.
Figure 58 shows that a ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in the right range. This condition is easily avoided through either the use of an enable signal, or by increasing the soft-start time with CSS/NR.
There is no sequencing requirement between the BIAS, IN, and EN pins in the TPS7A83A.
The TPS7A83A output can be negatively biased to the absolute maximum rating, without affecting start-up condition.
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the body diode on the pass element instead of the normal conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device resulting from risks of electro-migration and excess heat being dissipated across the device. If the current flow gets high enough, a latch-up condition can be entered.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V:
If excessive reverse current flow is expected in the application, then external protection must be used to protect the device. Figure 59 shows one approach of protecting the device.
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. Use Equation 11 to approximate PD:
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. According to Equation 12, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB, device package, and the temperature of the ambient air (TA). Equation 13 rewrites Equation 12 for output current.
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the table and are used in accordance with Equation 14.
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. As shown in Figure 60, the recommended area for continuous operation for a linear regulator can be separated into the following parts:
The TPS7A83A uses the ANY-OUT configuration to regulate a 2-A load requiring good PSRR at high frequency with low-noise at 0.9 V using a 1.2-V input voltage and a 5-V bias supply. Figure 67 provides a schematic for this typical application circuit.
For this design example, use the parameters listed in Table 13 as the input parameters.
|Input voltage||1.2 V, ±3%, provided by the dc-dc converter switching at 500 kHz|
|Bias voltage||5 V, ±5%|
|Output voltage||0.9 V, ±1%|
|Output current||2 A (maximum), 100 mA (minimum)|
|RMS noise, 10 Hz to 100 kHz||< 10 µVRMS|
|PSRR at 500 kHz||> 40 dB|
|Start-up time||< 25 ms|
At 2 A, the dropout of the TPS7A83A has 180-mV maximum dropout over temperature, thus a 400-mV headroom is sufficient for operation over both input and output voltage accuracy. The bias rail is provided for better performance for the LILO conditions. As per Table 13, the PSRR is greater than 40 dB in these conditions and noise is less than 10 µVRMS.
The ANY-OUT internal resistor network is also used for maximum accuracy.
To achieve 0.9 V on the output, the 100mV pin is grounded. Equation 15 describes how the voltage value of 100 mV is added to the 0.8-V internal reference voltage for VOUT(nom) equal to 0.9 V.
Input and output capacitors are selected in accordance with the External Component Selection section. Ceramic capacitors of 10 µF for the input and one 22-µF capacitor for the output are selected.
To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. Equation 16 calculates this value.
At the 2-A maximum load, the internal power dissipation is 0.6 W and corresponds to a 26.04°C junction temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient temperature, the junction temperature is at 94.06°C. To further minimize noise, a feed-forward capacitor (CFF) of 10 nF is selected.