SBVS304A June 2017 – November 2017 TPS7A83A
The TPS7A83A is a high-current (2 A), low-noise (4.4 µVRMS), high-accuracy (0.75%), low-dropout linear voltage regulator (LDO). These features make the device a robust solution to solve many challenging problems in generating a clean, accurate power supply.
|VOLTAGE REGULATION||SYSTEM START-UP||INTERNAL PROTECTION|
|High accuracy||Programmable soft-start||Foldback current limit|
|Low-noise, high-PSRR output||No sequencing requirement between BIAS, IN, and EN||Thermal shutdown|
|Fast transient response||Power-good output|
|Start-up with negative bias on OUT|
Overall, these features make the TPS7A83A the component of choice because of the versatility and ability of the device to generate a supply for most applications.
NOTE:For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual resistance can vary significantly from the numbers listed.
As Figure 43 shows, an LDO functions as a class-B amplifier in which the input signal is the internal reference voltage (VREF). VREF is designed to have a very low bandwidth at the input to the error amplifier through the use of a low-pass filter (VNR/SS).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes from the combination of the output capacitor and pass element. The pass element also presents a high input impedance to the source voltage when operating as a current source. A positive LDO can only source current because of the class-B architecture.
This device achieves a maximum of 0.75% output voltage accuracy primarily because of the high-precision band-gap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation required by the device to regulate the output voltage at a given current level, thereby improving system efficiency. These features combine to make this device a good approximation of an ideal voltage source.
NOTE:VOUT = VREF × (1 + R1 / R2).
The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output current (load transient) resulting from the LDO high-input impedance and low output-impedance across frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a low internal noise-floor (en), the LDO approximates an ideal power supply in ac (small-signal) and large-signal conditions.
The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor (CNR/SS) and feed-forward capacitor (CFF) easily reduce the device noise floor and improve PSRR; see Optimizing Noise and PSRR for more information on optimizing the noise and PSRR performance.
In many different applications, the power-supply output must turn on within a specific window of time to either ensure proper operation of the load or to minimize the loading on the input supply or other sequencing requirements. The LDO start-up is well-controlled and user-adjustable, solving the demanding requirements faced by many power-supply design engineers in a simple fashion.
Soft-start directly controls the output start-up time and indirectly controls the output current during start-up (in-rush current).
Figure 44 shows that the external capacitor at the NR/SS pin (CNR/SS) sets the output start-up time by setting the rise time of the internal reference (VNR/SS).
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of the high power levels inherent in a PDN, and the variations between all of the supplies. Figure 45 and Table 2 show how the LDO turnon and turnoff time are set by the enable circuit (EN) and undervoltage lockout circuits (UVLO1,2(IN) and UVLOBIAS).
|INPUT VOLTAGE||BIAS VOLTAGE||ENABLE STATUS||LDO STATUS||ACTIVE DISCHARGE||POWER GOOD|
|VIN ≥ VUVLO_1,2(IN)||VBIAS ≥ VUVLO(BIAS)||EN = 1||On||Off||PG = 1 when VOUT ≥ VIT(PG)|
|EN = 0||Off||On||PG = 0|
|VBIAS < VUVLO(BIAS) + VHYS(BIAS)||EN = don't care||Off||On (1)|
|VIN < VUVLO_1,2(IN) – VHYS1,2(IN)||BIAS = don't care||Off|
|IN = don't care||VBIAS ≥ VUVLO(BIAS)||Off|
The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN ≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. Connect EN to VIN or VBIAS if enable functionality is not desired.
The UVLO circuits respond quickly to glitches on IN or BIAS and attempts to disable the output of the device if either of these rails collapse.
The local input capacitance prevents severe brownouts in most applications; see the Undervoltage Lockout (UVLO) section for more details.
When either EN or UVLO is low, the device connects a resistor of several hundred ohms from VOUT to GND, discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUT > VIN, which can cause damage to the device (when VOUT > VIN + 0.3 V); see the Reverse Current section for more details.
The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals when the output nears the nominal value. PG can be used to signal other devices in a system when the output voltage is near, at, or above the set output voltage (VOUT(nom)). Figure 46 shows a simplified schematic.
The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFF) delays the output voltage and, because the PG circuit monitors the FB pin, the PG signal can indicate a false positive. A simple solution to this scenario is to use an external voltage detector device, such as the TPS3890; see the Feed-Forward Capacitor (CFF) section for more information.
In many applications, fault events can occur that damage devices in the system. Short circuits and excessive heat are the most common fault events for power supplies. The TPS7A83A implements circuitry to protect the device and its load during these events. Continuously operating in these fault conditions or above a junction temperature of 125°C is not recommended because the long-term reliability of the device is reduced.
The internal current limit circuit is used to protect the LDO against high load-current faults or shorting events. During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased load impedance. Thermal shutdown can activate during a current limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended.
The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current limit or high ambient temperature.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal shutdown temperature. The output turns on again after TJ decreases below the falling thermal shutdown temperature.
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be greater than or equal to Tsd, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can cycle on and off when thermal shutdown is reached under these conditions.
Continuously triggering thermal shutdown can degrade long-term reliability.
Table 3 provides a quick comparison between the regulation and disabled operation.
|Regulation(1)||VIN > VOUT(nom) + VDO||VBIAS ≥ VUVLO(BIAS)(3)||VEN > VIH(EN)||IOUT < ICL||TJ ≤ TJ(maximum)|
|Disabled(2)||VIN < VUVLO_1,2(IN)||VBIAS < VUVLO(BIAS)||VEN < VIL(EN)||TJ > Tsd|
|Current-limit operation||IOUT ≥ ICL|
The device regulates the output to the nominal output voltage when all the conditions in Table 3 are met.
When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is actively discharged to ground by an internal resistor from the output to ground. See the Active Discharge section for additional information.