SBVS304A June   2017  – November 2017 TPS7A83A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configurations and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft-Start (NR/SS)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Adjustable Operation
        2. 8.1.1.2 ANY-OUT Programmable Output Voltage
        3. 8.1.1.3 ANY-OUT Operation
        4. 8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
        5. 8.1.1.5 Recommended Capacitor Types
        6. 8.1.1.6 Input and Output Capacitor Requirements (CIN and COUT)
        7. 8.1.1.7 Feed-Forward Capacitor (CFF)
        8. 8.1.1.8 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Soft-Start (NR/SS)
          1. 8.1.2.1.1 Inrush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLO)
        3. 8.1.2.3 Power-Good (PG) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Output Voltage Noise
        3. 8.1.3.3 Optimizing Noise and PSRR
          1. 8.1.3.3.1 Charge Pump Noise
        4. 8.1.3.4 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUT)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 8.1.5 Sequencing Requirements
      6. 8.1.6 Negatively Biased Output
      7. 8.1.7 Reverse Current
      8. 8.1.8 Power Dissipation (PD)
        1. 8.1.8.1 Estimating Junction Temperature
        2. 8.1.8.2 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Models
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage IN, BIAS, PG, EN –0.3 7.0 V
IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs) –0.3 7.5
SNS, OUT –0.3 VIN + 0.3(2)
NR/SS, FB –0.3 3.6
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V –0.3 VOUT + 0.3
Current OUT Internally limited A
PG (sink current into device) 5 mA
Operating junction temperature, TJ –55 150 °C
Storage temperature, Tstg –55 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage range 1.1 6.5 V
VBIAS BIAS supply voltage range(1) 3.0 6.5 V
VOUT Output voltage range(2) 0.8 5.2 V
VEN Enable voltage range 0 VIN V
IOUT Output current 0 2 A
CIN Input capacitor 10 22 µF
COUT Output capacitor 22 22 µF
CBIAS BIAS capacitor 10 (5) µF
RPG Power-good pullup resistance 10 100
CNR/SS NR/SS capacitor 10 nF
CFF Feed-forward capacitor 10 nF
R1 Top resistor value in feedback network for adjustable operation 12.1(3)
R2 Bottom resistor value in feedback network for adjustable operation 160(4)
TJ Operating junction temperature –40 125 °C
The BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
This output voltage range does not include device accuracy or accuracy of the feedback resistors.
The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R1 value.
The upper limit for the R2 resistor is to ensure accuracy by making the current through the feedback network much larger than the leakage current into the feedback node.
If BIAS is used, a 10-µF capacitor is required.  If BIAS is not used, a capacitor on the BIAS pin is not needed.

Thermal Information

THERMAL METRIC(1) TPS7A83A UNIT
RGR (VQFN) RGW (VQFN)
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 43.4 33.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.8 24.9 °C/W
RθJB Junction-to-board thermal resistance 17.6 13.0 °C/W
ψJT Junction-to-top characterization parameter 0.8 0.4 °C/W
ψJB Junction-to-board characterization parameter 17.6 13 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.4 3.9 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.3 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V(2), OUT connected to 50 Ω to GND(3), VEN = 1.1 V, CIN = 10 μF, COUT = 22 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); ypical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range(1) 1.1 6.5 V
VBIAS Bias supply voltage range(1) VIN = 1.1 V 3.0 6.5 V
VFB Feedback voltage 0.8 V
VNR/SS NR/SS pin voltage 0.8 V
VUVLO1(IN) Input supply UVLO with BIAS VIN rising with VBIAS = 3.0 V 1.02 1.085 V
VHYS1(IN) VUVLO1(IN) hysteresis VBIAS = 3.0 V 320 mV
VUVLO2(IN) Input supply UVLO without BIAS VIN rising 1.31 1.39 V
VHYS2(IN) VUVLO2(IN) hysteresis 253 mV
VUVLO(BIAS) Bias supply UVLO VBIAS rising, VIN = 1.1 V 2.83 2.9 V
VHYS(BIAS) VUVLO(BIAS) hysteresis VIN = 1.1 V 290 mV
VOUT Output voltage Range Using the ANY-OUT pins 0.8 – 1.0% 3.95 + 1.0% V
Using external resistors(4) 0.8 – 1.0% 5.2 + 1.0%
Accuracy(4)(5) 0.8 V ≤ VOUT ≤ 5.2 V,
5 mA ≤ IOUT ≤ 2 A, 1.4 V ≤ VIN ≤ 6.5 V
–1.0% 1.0%
Accuracy with BIAS 1.1V ≤ VIN ≤ 2.2 V, 0.8V ≤ VOUT ≤ 1.9 V,  
5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V
–0.75% 0.75%
ΔVOUT/
ΔVIN
Line regulation IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.03 mV/V
ΔVOUT/
ΔIOUT
Load regulation 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V
0.07 mV/A
5 mA ≤ IOUT ≤ 2 A 0.08
5 mA ≤ IOUT ≤ 2 A, VOUT = 5.2 V 0.04
VDO Dropout voltage VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3% 200 mV
VIN = 1.1 V, VBIAS = 5 V,
IOUT = 2 A, VFB = 0.8 V – 3%
125
VIN = 5.3 V, IOUT = 2 A, VFB = 0.8V – 0.3% 200 mV
VIN = 5.5 V, IOUT = 2 A, VFB = 0.8V – 0.3% 300
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V
2.8 3.3 3.8 A
ISC Short-circuit current limit RLOAD = 20 mΩ 1.0 A
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 2.8 4 mA
VIN = 1.4 V, IOUT = 2 A 3.7 5
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V 25 µA
IEN EN pin current VIN = 6.5 V, VEN = 0 V and 6.5 V –0.1 0.1 µA
IBIAS BIAS pin current VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 2 A
2.3 3.5 mA
VIL(EN) EN pin low-level input voltage
(disable device)
0 0.5 V
VIH(EN) EN pin high-level input voltage
(enable device)
1.1 6.5 V
VIT(PG) PG pin threshold For falling VOUT 82% × VOUT 88% × VOUT 93% × VOUT V
VHYS(PG) PG pin hysteresis For rising VOUT 2% × VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA
(current into device)
0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VIN = 6.5 V 4.0 6.2 9.0 µA
IFB FB pin leakage current VIN = 6.5 V –100 100 nA
PSRR Power-supply rejection ratio VIN – VO UT = 0.4 V,
IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF,
COUT = 22 μF
f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V
42 dB
f = 500 kHz, VOUT = 0.8 V, VBIAS = 5.0 V 39
f = 10 kHz,
VOUT = 5.0 V
40
f = 500 kHz, VOUT = 5.0 V 25
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 2 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 22 μF
4.4 μVRMS
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 2 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 22 μF
7.7
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
TJ Operating junction temperature –40 125 °C
The BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the expected VOUT value set by the external feedback resistors.
This 50-Ω load is disconnected when the test conditions specify an IOUT value.
When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
The device is not tested under conditions where VIN > VOUT + 2.5 V and IOUT = 2 A because the power dissipation is higher than the maximum rating of the package.

Typical Characteristics

at TA = 25°C, VIN = 1.4 V or VIN = VOUT(nom) + 0.3 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V, VEN = 1.1 V, CIN = 10 μF, COUT = 22 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
TPS7A83A Fig1-PSRRvsFrequencyandIout.gif
VIN = 1.1 V, VBIAS = 5 V,
COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 1. PSRR vs Frequency and IOUT
TPS7A83A Fig3-PSRRvsFrequencyandVbias.gif
VIN = 1.4 V, IOUT = 1 A,
COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 3. PSRR vs Frequency and VBIAS
TPS7A83A Fig5-PSRRvsFrequencyandVout=Vin_plus0.3V.gif
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 2 A,
COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 5. PSRR vs Frequency and VOUT With BIAS
TPS7A83A Fig7-PSRRvsFrequencyandCout.gif
VIN = VOUT + 0.3 V, VOUT = 1 V, VBIAS = 5 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF
Figure 7. PSRR vs Frequency and COUT
TPS7A83A Fig9-OutputVoltageNoisevsOutputVoltage.gif
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
COUT = 22 μF, CBIAS = 10 μF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 9. Output Voltage Noise vs Output Voltage
TPS7A83A Fig11-OutputVoltageNoisevsFreqvsVin.gif
IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF,
CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 11. Output Noise vs Frequency and Input Voltage
TPS7A83A Fig13-OutputVoltageNoisevsFreqvsCff.gif
VIN = 5.3V, VOUT = 5V, VBIAS = 5 V, IOUT = 2 A,
COUT = 22 μF, CBIAS = 10 μF, CNR/SS = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 13. Output Noise vs Frequency and CFF
TPS7A83A Startup_Vs_Cnr.gif
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5 V, IOUT = 2 A,
COUT = 22 μF, CBIAS = 10 μF, CFF = 10 nF
Figure 15. Start-Up Waveform vs Time and CNR/SS
TPS7A83A Fig17-LoadtransientVout=5VwithoutBias.gif
IOUT, DC = 100 mA, COUT = 22 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
Figure 17. Load Transient vs Time for VOUT = 5 V
TPS7A83A Fig19-LoadtransientVout=5VvsDCload.gif
VIN = 5.3 V, VBIAS = 5 V, COUT = 22 μF, CBIAS = 10 μF,
VOUT = 5 V, CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
Figure 19. Load Transient vs Time and DC Load
TPS7A83A D024-sbvs304-01.gif
IOUT = 2 A, VBIAS = 6.5 V
Figure 21. Dropout Voltage vs Input Voltage With BIAS
TPS7A83A D026-sbvs304-01.gif
VIN = 1.1 V, VBIAS = 3 V
Figure 23. Dropout Voltage vs Output Current With BIAS
TPS7A83A D025_SBVS304.gif
IOUT = 100 mA to 2 A
Figure 25. Load Regulation vs Output Voltage
TPS7A83A D027_SBVS304.gif
VIN = 3.8 V
Figure 27. Load Regulation (3.3-V Output)
TPS7A83A D011_SBVS267.gif
VOUT = 0.8 V, IOUT = 5 mA
Figure 29. Line Regulation
TPS7A83A D014_SBVS267.gif
IOUT = 5 mA
Figure 31. Line Regulation (5-V Output)
TPS7A83A D016_SBVS267.gif
VIN = 1.1 V, IOUT = 5 mA
Figure 33. BIAS Pin Current vs Bias Voltage
TPS7A83A D018_SBVS267.gif
VIN = 1.1 V
Figure 35. Shutdown Current vs Bias Voltage
TPS7A83A UVLO_Vin.gif
Figure 37. VIN UVLO vs Temperature
TPS7A83A D023_SBVS267.gif
VIN = 1.4 V, 6.5 V
Figure 39. Enable Threshold vs Temperature
TPS7A83A D025_SBVS267.gif
VIN = 6.5 V
Figure 41. PG Voltage vs PG Current Sink
TPS7A83A Fig2-PSRRvsFrequencyandVin.gif
IOUT = 2 A, VBIAS = 5 V,
COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 2. PSRR vs Frequency and VIN With BIAS
TPS7A83A Fig4-PSRRvsFrequencyandVin_Vbias.gif
IOUT = 1 A,
COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 4. PSRR vs Frequency and VIN
TPS7A83A Fig6-PSRRvsFrequencyandVin,Vout=3.3V.gif
IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF,
CFF = 10 nF
Figure 6. PSRR vs Frequency and VIN for VOUT = 3.3 V
TPS7A83A 7a84_Bias_PSRR.gif
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 2 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 8. VBIAS PSRR vs Frequency
TPS7A83A Fig10-OutputVoltageNoisevsFreqvsVout.gif
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤ 2.2 V, IOUT = 2 A, COUT = 22 μF, CBIAS = 10 μF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 10. Output Noise vs Frequency and Output Voltage
TPS7A83A Fig12-OutputVoltageNoisevsFreqvsCnrss.gif
VIN = 1.1V, VOUT = 0.8V, VBIAS = 5 V, IOUT = 2 A, COUT = 22 μF,
CBIAS = 10 μF, CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 12. Output Noise vs Frequency and CNR/SS
TPS7A83A Fig14-OutputVoltageNoisevsFreqvsCnrss-CffVout=5V.gif
IOUT = 2 A, COUT = 22 μF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 14. Output Noise at 5-V Output
TPS7A83A Fig16-LoadtransientVout=0.8VwithandwithoutBias.gif
IOUT, DC = 100 mA, slew rate = 1 A/μs, CNR/SS = 10 nF,
COUT = 22 μF, CBIAS = 10 μF
Figure 16. Load Transient vs Time for VOUT = 0.8 V
TPS7A83A Fig18-LoadtransientVout=5VvsSlewRate.gif
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 2 A,
COUT = 22 μF, CNR/SS = CFF = 10 nF
Figure 18. Load Transient vs Time and Slew Rate
TPS7A83A D023-sbvs304-01.gif
IOUT = 2 A
Figure 20. Dropout Voltage vs Input Voltage Without BIAS
TPS7A83A D025-sbvs304-01.gif
VIN = 1.4 V
Figure 22. Dropout Voltage vs Output Current Without BIAS
TPS7A83A D027-sbvs304-01.gif
VIN = 5.5 V
Figure 24. Dropout Voltage vs Output Current (High VIN)
TPS7A83A D026_SBVS304.gif
VIN = 1.4 V
Figure 26. Load Regulation
TPS7A83A D028_SBVS304.gif
VIN = 5.5 V
Figure 28. Load Regulation (5-V Output)
TPS7A83A D012_SBVS267.gif
VOUT = 0.8 V, VIN = 1.1 V, IOUT = 5 mA, VBIAS = 5 V
Figure 30. Line Regulation With BIAS
TPS7A83A D015_SBVS267.gif
VBIAS = 0 V, IOUT = 5 mA
Figure 32. Ground Pin Current vs Input Voltage
TPS7A83A D017_SBVS267.gif
VBIAS = 0 V
Figure 34. Shutdown Current vs Input Voltage
TPS7A83A D019_SBVS267.gif
VBIAS = 0 V
Figure 36. INR/SS Current vs Input Voltage
TPS7A83A D022_SBVS267.gif
VIN = 1.1 V
Figure 38. VBIAS UVLO vs Temperature
TPS7A83A D024_SBVS267.gif
Figure 40. PG Voltage vs PG Current Sink
TPS7A83A D026_SBVS267.gif
Figure 42. PG Threshold vs Temperature