SBVS318B July 2017 – January 2019 TPS7A92
PRODUCTION DATA.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits. The TPS7A92 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based clocking circuits where minimum phase noise is all important, or in test and measurement systems where even small power-supply noise fluctuations can distort instantaneous measurement accuracy.
The TPS7A92 includes a low-noise reference ensuring minimal output noise in normal operation. Further improvements can be made by adding a noise reduction capacitor (CNR/SS), a feedforward capacitor (CFF), or a combination of the two. See the Noise-Reduction and Soft-Start Capacitor (CNR/SS) and Feed-Forward Capacitor (CFF) sections for additional design information.
For more information on noise and noise measurement, see the How to Measure LDO Noise white paper.