SLVSCP3C January 2015 – July 2016 TPS7B4253-Q1
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS7B4253-Q1 device is a 300-mA low-dropout tracking regulator with ultralow tracking tolerance. The PSpice transient model is available for download on the product folder and can be used to evaluate the basic function of the device.
Figure 27 shows the typical application circuit for the TPS7B4253-Q1 device (using the HTSSOP package as an example). Different values of external components can be used depending on the end application. An application may require a larger output capacitor during fast load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with a dielectric of type X5R or X7R.
For this design example, use the parameters listed in Table 1 as the design parameters.
|DESIGN PARAMETER||EXAMPLE VALUE|
|Input voltage||4 to 40 V|
|Output voltage||1.5 to 40 V|
|Enable voltage||2 to 40 V|
|ADJ voltage||1.5 to 18 V|
|Output capacitor||10 to 500 µF|
|Output capacitor ESR range||0.001 to 20 Ω|
To begin the design process, determine the following:
The device requires an input decoupling capacitor, the value of which depends on the application. The typical recommended value for the decoupling capacitor is 2.2 µF. The voltage rating must be greater than the maximum input voltage.
To ensure the stability of the TPS7B4253-Q1 device, the device requires an output capacitor with a value in the range from 10 µF to 500 µF and with an ESR range from 0.001 Ω to 20 Ω when the FB pin is directly connected to the OUT pin. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient response.
To achieve an output voltage higher than the reference voltage, a resistor divider is connected between the OUT pin and the FB pin. In this case, a 47-nF feed forward capacitor must be connected between the OUT and FB pins for loop stability. The ESR of the output capacitor must be from 0.001 Ω to 10 Ω.
When multiple capacitors (two or more) are connected in parallel at the OUT pin, the ESR range of each output capacitor must be from 0.001 Ω to 3 Ω for loop stability.
In case the FB pin is shorted to ground, the TPS7B4253-Q1 device functions as a power switch with no need for the output capacitor.
|VIN = 6 to 40 V||VADJ = 5 V||C(OUT) = 10 µF|
|IOUT = 100 mA, 20 µs/div|
As shown in Figure 29, by connecting the FB pin to the GND pin, the TPS7B4253-Q1 device can be used as a high-side switch with current-limit, thermal shutdown, output short-to-battery, and reverse polarity protection. The switching on and off of the device is then controlled through the EN and ADJ pins.
With an accurate voltage rail, the TPS7B4253-Q1 device can be used as an LDO with ultrahigh-accuracy output voltage by configuring the device as shown in Figure 30.
For example, assume the reference voltage is a 5-V rail with 0.5% accuracy. Because the tracking accuracy between the ADJ and OUT pins is specified below 4 mV across temperature, the output accuracy of the TPS7B4253-Q1 device can be calculated with Equation 4.