SLVSDI1B April   2016  – June 2016 TPS7B4254-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Short-Circuit and Overcurrent Protection
      2. 7.3.2 Integrated Inductive Clamp Protection
      3. 7.3.3 OUT Short-to-Battery and Reverse-Polarity Protection
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Thermal Protection
      6. 7.3.6 Regulated Output (OUT)
      7. 7.3.7 Adjustable Output Voltage (FB and ADJ)
        1. 7.3.7.1 OUT Voltage Equal to the Reference Voltage
        2. 7.3.7.2 OUT Voltage Higher Than Reference Voltage
        3. 7.3.7.3 Output Voltage Lower Than Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application With Output Voltage Equal to the Reference Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High-Accuracy LDO
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Unregulated input voltage IN(2) –40 45 V
Regulated output voltage OUT(2)(3) –1 45 V
Voltage difference between the input and output IN – OUT –40 45 V
Reference voltage ADJ(2) –0.3 45 V
Feedback input voltage for the tracker FB(2) –1 45 V
Reference voltage minus the input voltage ADJ – IN(4) 18 V
Operating junction temperature, TJ –40 150 ºC
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND pin.
(3) An internal diode is connected between the OUT and GND pins with 600-mA dc current capability for inductive clamp protection.
(4) When the (ADJ – IN) voltage is higher than 18 V, the (ADJ – OUT) voltage should be maintained lower than 18 V, otherwise the device can be damaged.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) All pins except NC ±4000 V
NC pins ±2000
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Unregulated input voltage(2) 4 40 V
VADJ Reference input voltage 2 18 V
VFB Feedback input voltage for the tracker 2 18 V
VOUT Regulated output voltage 2 40 V
COUT Output capacitor requirements(3) 10 500 µF
Output ESR requirements(4) 0.001 20 Ω
TJ Operating junction temperature –40 150 ºC
(1) Within the functional range the device operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related Electrical Characteristics table.
(2) VIN > VADJ + VDROPOUT
(3) The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%. When a resistor divider is connected between the OUT and FB pins (the output voltage is higher than reference voltage), a 47-nF feedforward capacitor is required to be connected between the OUT and FB pins for loop stability, and the ESR range of the output capacitor is required to be from 0.001 to 10 Ω.
(4) Relevant ESR value at f = 10 kHz

6.4 Thermal Information

THERMAL METRIC(1) TPS7B4254-Q1 UNIT
DDA (HSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 45.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.1 °C/W
RθJB Junction-to-board thermal resistance 27 °C/W
ψJT Junction-to-top characterization parameter 8.2 °C/W
ψJB Junction-to-board characterization parameter 26.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VIN = 13.5 V, VADJ ≥ 2 V, TJ = –40ºC to 150ºC, over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN(UVLO) IN undervoltage detection VIN rising 3.65 V
VIN falling 2.8 V
ΔVOUT Output voltage tracking accuracy(1) IOUT = 100 μA to 150 mA, VIN = 4 to 40 V
VADJ < VIN – 1 V
2 V < VADJ < 18 V		 –4 4 mV
ΔVOUT(ΔIO) Load regulation, steady-state IOUT = 0.1 to 150 mA, VADJ= 5 V 4 mV
ΔVOUT(ΔVI) Line regulation, steady-state IOUT = 10 mA, VIN = 6 to 40 V, VADJ = 5 V 4 mV
PSRR Power-supply ripple rejection frip = 100 Hz, Vrip = 0.5 VPP, COUT = 10 μF, IOUT = 100 mA 70 dB
VDROPOUT Dropout voltage (VDROPOUT = VIN – VOUT) IOUT = 100 mA, VIN = VADJ ≥ 4 V(2) 160 260 mV
IOUT(LIM) Output current limitation VADJ = 5 V, OUT short to GND 151 450 520 mA
IR(IN) Reverse current at IN VIN = 0 V, VOUT = 40 V, VADJ = 5 V –2 0 µA
IR(–IN) Reverse current at negative IN VIN = –40 V, VOUT = 0 V, VADJ = 5 V –10 µA
TSD Thermal shutdown temperature 175 ºC
TSD_hys Thermal shutdown hysteresis 15 ºC
IQ Current consumption 4 V ≤ VIN ≤ 40 V, VADJ = 0 V 2 4 µA
4 V ≤ VIN ≤ 40 V, VADJ = 5 V, IOUT < 100 µA 60 100 µA
4 V ≤ VIN ≤ 40 V, VADJ = 5 V, IOUT < 150 mA 210 260 µA
IQ(DROPOUT) Current consumption in dropout region VIN = VADJ = 5 V, IOUT = 100 μA 70 140 µA
IADJ Reference input current VADJ = VFB = 5 V 5.5 µA
VADJ(LOW) Reference low signal valid VOUT = 0 V 0 0.7 V
VADJ(HIGH) Reference high signal valid |VOUT – VADJ| < 4 mV 2 18 V
IFB FB bias current VADJ = VFB = 5 V 0.5 µA
(1) The tracking accuracy is specified when the FB pin is directly connected to the OUT pin which means VADJ = VOUT, external resistor divider variance is not included.
(2) Measured when the output voltage, VOUT, has dropped 10 mV from the nominal value.

6.6 Typical Characteristics

TPS7B4254-Q1 D001_SLVSDI1.gif
V
Figure 1. Tracking Accuracy vs Ambient Temperature
TPS7B4254-Q1 D003_SLVSDI1.gif
V
Figure 3. Load Regulation
TPS7B4254-Q1 D005_SLVSDI1.gif
VIN = VADJ = 4 V IOUT = 100 mA
Figure 5. Dropout Voltage vs Ambient Temperature
TPS7B4254-Q1 D007_SLVSDI1.gif
V
Figure 7. Shutdown Current vs Ambient Temperature
TPS7B4254-Q1 D009_SLVSDI1.gif
V
Figure 9. Quiescent Current vs Ambient Temperature
TPS7B4254-Q1 D011_SLVSDI1.gif
COUT = 10 µF IOUT = 1 mA TA = 25°C
VIN = 14 V VADJ = 5 V
Figure 11. PSRR
TPS7B4254-Q1 D013_SLVSDI1.gif
VFB = VOUT
Figure 13. ESR Stability vs Load Capacitance
TPS7B4254-Q1 D015_SLVSDI1.gif
V
V
Figure 15. ESR Stability vs Load Capacitance (Multiple Output Capacitors in parallel)
TPS7B4254-Q1 D017_SLVSDI1.gif
VIN = 40 to 6 V VADJ = 5 V COUT = 10 µF
IOUT = 10 mA 40 µs/div
Figure 17. 40-V to 6-V Line Transient
TPS7B4254-Q1 D019_SLVSDI1.gif
VIN = 40 to 6 V VADJ = 5 V COUT = 10 µF
IOUT = 100 mA 40 µs/div
Figure 19. 40-V to 6-V Line Transient
TPS7B4254-Q1 D021_SLVSDI1.gif
VIN = 14 V VADJ = 5 V COUT = 10 µF
IOUT = 100 mA to 10 mA 100 µs/div
Figure 21. 100-mA to 10-mA Load Transient
TPS7B4254-Q1 D002_SLVSDI1.gif
V
Figure 2. Line Regulation
TPS7B4254-Q1 D004_SLVSDI1.gif
VIN = VADJ = 4 V
Figure 4. Dropout Voltage vs Output Current
TPS7B4254-Q1 D006_SLVSDI1.gif
V
Figure 6. Current Limit (IOUT(LIM)) vs Ambient Temperature
TPS7B4254-Q1 D008_SLVSDI1.gif
V
Figure 8. Quiescent Current vs Output Current
TPS7B4254-Q1 D010_SLVSDI1.gif
VADJ = 5 V
Figure 10. Quiescent Current vs Input Voltage
TPS7B4254-Q1 D012_SLVSDI1.gif
COUT = 10 µF IOUT = 100 mA TA = 25°C
VIN = 14 V VADJ = 5 V
Figure 12. PSSR
TPS7B4254-Q1 D014_SLVSDI1.gif
VFB < VOUT
Figure 14. ESR Stability vs Load Capacitance
TPS7B4254-Q1 D016_SLVSDI1.gif
VIN = 6 to 40 V VADJ = 5 V COUT = 10 µF
IOUT = 10 mA 40 µs/div
Figure 16. 6-V to 40-V Line Transient
TPS7B4254-Q1 D018_SLVSDI1.gif
VIN = 6 to 40 V VADJ = 5 V COUT = 10 µF
IOUT = 100 mA 40 µs/div
Figure 18. 6-V to 40-V Line Transient
TPS7B4254-Q1 D020_SLVSDI1.gif
VIN = 14 V VADJ = 5 V COUT = 10 µF
IOUT = 10 mA to 100 mA 100 µs/div
Figure 20. 10-V to 100-mA Load Transient