SLVSDW6C April   2017  – April 2021 TPS7H1101A-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Power Good (PG)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable/Disable
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Stability
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Adjustable Output Voltage (Feedback Circuit)
        2. 8.2.1.2 PCL
        3. 8.2.1.3 High-Side Current Sense
        4. 8.2.1.4 Current Foldback
        5. 8.2.1.5 Transient Response
        6. 8.2.1.6 Current Sharing
        7. 8.2.1.7 Compensation
        8. 8.2.1.8 Output Noise
        9. 8.2.1.9 Capacitors
      2. 8.2.2 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.3 High-Side Current Sense

Figure 8-4 shows the cascode NMOS current mirror. VCS must be ≥ 0.3 V for proper biasing. Additionally VCS must be greater than 0.9 · VREF (0.544 V) if foldback current limiting is intended to be enabled. The following example shows the typical calculation of RCS.

Equation 4. GUID-DB8A246A-41C3-4798-9F04-B54822F9EDB0-low.gif
Equation 5. GUID-649ADA41-3C47-4BCF-966D-E72FFF015C67-low.gif

where

  • ILOAD is the output load current
  • CSR is the current sense ratio
  • Ioffset is internal keep-alive bias current times CSR
  • Ioffset = 5 µA · CSR

When VIN = 2.3 V, select VCS = 2.05 V, ILOAD = 3 A, CSR = 52000, and Ioffset = 0.26 A, then ICS = 62.69 µA and RCS = 3.99 kΩ.

GUID-ACC9AC51-D75F-47AA-90B1-25B743A23612-low.gifFigure 8-4 Cascode NMOS Current Mirror

For TPS7H1101A-SP, Figure 8-5 shows a typical curve VCS vs IOUT for VIN = 2.28 V and RCS = 3.65 kΩ. A resistor connected from the CS terminal to VIN indicates voltage proportional to the output current.

Monitoring current in the CS terminal (ICS vs ILOAD) indicates the current sense ratio between the main PMOSFET and the current sense MOSFET as shown in Figure 8-6. Additionally Figure 8-6 shows the linearity of the CSR ratio across VCS pin voltage range of 0.3 V to VIN. VCS must be ≥ 0.3-V minimum to keep circuit properly biased.

Figure 8-7 shows ILOAD vs ICS across the full range of CSR values.

GUID-FE0EFE95-8A90-42AC-8503-F153407F93B9-low.gif
VIN = 2.3 VVOUT = 1.8 Vy = –0.078x + 2.2853
Figure 8-5 VCS (V) vs ILOAD (A)
GUID-33F405C7-F33F-49A0-BA14-126A28F5E258-low.gifFigure 8-7 IOUT (A) vs ICS (A)
GUID-D7C6A4D4-8220-45F8-B021-647618148A30-low.gif
VIN = 2.3 VVOUT = 1.8 V
Figure 8-6 IOUT (A) vs ICS (A)