SLVSFL2A May   2021  – August 2021 TPS7H4002-SP

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Enable and Adjust UVLO
      8. 7.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 7.3.9  Slow Start (SS/TR)
      10. 7.3.10 Power Good (PWRGD)
      11. 7.3.11 Sequencing (SS/TR)
      12. 7.3.12 Output Overvoltage Protection (OVP)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Turn-On Behavior
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
      2. 7.4.2 Continuous Current Mode (CCM) Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Slow Start Capacitor Selection
        5. 8.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 8.2.2.6 Output Voltage Feedback Resistor Selection
        7. 8.2.2.7 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Sequencing (SS/TR)

Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins.

The sequential method is shown in Figure 7-5 using two TPS7H4002-SP devices. The power good of the first device is coupled to the EN pin of the second device, which enables the second power supply after the primary supply reaches regulation.

Figure 7-5 Sequential Start-Up Sequence

Figure 7-6 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must be doubled in Equation 5.

GUID-20210324-CA0I-GP4P-G8QR-FHW8XGKB8H3P-low.png Figure 7-6 Ratiometric Start-Up Sequence

Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network of R1 and R2 (shown in Figure 7-7) to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after, or at the same time as VOUT1. Equation 8 is the voltage difference between VOUT1 and VOUT2.

To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 6 and Equation 7 for ΔV. Equation 8 results in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset ( VSS-OFFSET, 30 mV) in the slow-start circuit and the offset created by the pullup current source (ISS = 2.5 μA) and tracking resistors, the VSS-OFFSET and ISS are included as variables in the equations.

To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9.

Equation 6. GUID-E475B8BF-41CE-46C8-A156-6471BB399909-low.gif
Equation 7. GUID-DDFB4723-5C0C-4CB9-BEEB-4E2857E06F51-low.gif
Equation 8. GUID-4247D739-C597-4A7E-9565-56E5C752423E-low.gif
Equation 9. GUID-E5262AC0-1F07-4475-BCE9-427E560336AB-low.gif
GUID-20210323-CA0I-7GVC-NN1L-P4KG1XSSFFGF-low.png Figure 7-7 Ratiometric and Simultaneous Start-Up Sequence