SLVSFL2A May   2021  – August 2021 TPS7H4002-SP

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Enable and Adjust UVLO
      8. 7.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 7.3.9  Slow Start (SS/TR)
      10. 7.3.10 Power Good (PWRGD)
      11. 7.3.11 Sequencing (SS/TR)
      12. 7.3.12 Output Overvoltage Protection (OVP)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Turn-On Behavior
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
      2. 7.4.2 Continuous Current Mode (CCM) Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Slow Start Capacitor Selection
        5. 8.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 8.2.2.6 Output Voltage Feedback Resistor Selection
        7. 8.2.2.7 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Parallel Operation

The TPS7H4002-SP can be configured in primary-secondary mode to provide 6-A output current as shown in Figure 8-2.

Figure 8-2 Parallel Configuration Showing Primary and Secondary

The design procedure to configure the primary-secondary operation using the internal oscillator is as follows:

  • The RT pin of the primary device must be left floating. This achieves two purposes: to set the frequency to 500 kHz (typical) using the internal oscillator and to configure the SYNC pin of the primary device as an output pin with a 500-kHz clock in phase respect to the internal oscillator of the primary device. For more details, see Adjustable Switching Frequency and Synchronization (SYNC) section.
  • The RT pin on secondary device should be connected to a resistor such that the frequency of the secondary device is within 5% of the primary's frequency, 500 kHz in this case. See Figure 7-4 for reference.
  • SYNC pin of the primary device must be connected to the SYNC pin of the secondary device.
  • Only a single feedback network is needed connected to the VSENSE pin of the primary device. Therefore, both VSENSE pins must be connected.
  • Only a single compensation network is needed connected to the COMP pin of the primary device. Therefore both COMP pins must be connected.
  • Only a single soft start capacitor is needed connected to the SS pin of the primary device. Therefore both SS pins must be connected.
  • Only a single enable signal (or resistor divider) is needed connected to the EN pin of the primary device. Therefore, both EN pins must be connected.
  • Since the primary device controls the compensation, soft start and enable networks, the factor of 2 must be taken into account when calculating the components associated with these pins.

The primary-secondary mode can also be implemented using an external clock. In such case, a different frequency other than 500 kHz can be used. When using an external clock, only the RT and SYNC pins configuration varies as follows:

  • RT pins of both primary and secondary device must be connected to a resistor matching the frequency of the external clock being used. See Figure 7-4 for reference.
  • The external clock is connected to the SYNC pin of the primary device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well.
  • An inverted clock (180° in phase respect to the primary device) must be connected to the SYNC pin of the secondary device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well.