SNVSBL0A November   2020  – December 2021 TPS7H4010-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Synchronous Step-Down Regulator
      2. 7.3.2  Auto Mode and FPWM Mode
      3. 7.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 7.3.4  Adjustable Output Voltage
      5. 7.3.5  Enable and UVLO
      6. 7.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 7.3.7  Soft Start and Voltage Tracking
      8. 7.3.8  Adjustable Switching Frequency
      9. 7.3.9  Frequency Synchronization and Mode Setting
      10. 7.3.10 Internal Compensation and CFF
      11. 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 7.3.12 Power-Good and Overvoltage Protection
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 DCM Mode
        3. 7.4.3.3 PFM Mode
        4. 7.4.3.4 Fault Protection Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setpoint
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Input Capacitors
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-Forward Capacitor
        7. 8.2.2.7  Bootstrap Capacitors
        8. 8.2.2.8  VCC Capacitor
        9. 8.2.2.9  BIAS
        10. 8.2.2.10 Soft Start
        11. 8.2.2.11 Undervoltage Lockout Setpoint
        12. 8.2.2.12 PGOOD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout For EMI Reduction
      2. 10.1.2 Ground Plane
      3. 10.1.3 Optimize Thermal Performance
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNP|30
  • KGD|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-1DD048FD-B163-40E2-96F0-E8377316B165-low.gif Figure 5-1 RNP Package
30-Pin WQFN 6 mm × 4 mm × 0.8 mm
(Top View)
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
1–5 SW P Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor and bootstrap capacitor.
6 CBOOT P Bootstrap capacitor connection for HS FET driver. Connect a high-quality 470-nF capacitor from this pin to the SW pin.
7 VCC P Output of internal bias supply. Used as supply to internal control circuits and drivers. Connect a high-quality 2.2-µF capacitor from this pin to GND. TI does not recommend loading this pin by external circuitry.
8 BIAS P Optional BIAS LDO supply input. TI recommends tying to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tie to an external 3.3-V or 5-V rail if available, to improve efficiency. BIAS pin voltage must not be greater than VIN. Tie to ground when not in use.
9 RT A Switching frequency setting pin. Place a resistor from this pin to ground to set the switching frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground.
10 SS/TRK A Soft-start control pin. Leave this pin floating for a fixed internal soft-start ramp. An external capacitor can be connected from this pin to ground to extend the soft start time. A 2-µA current sourced from this pin charges the capacitor to provide the ramp. Connect to external ramp for tracking. Do not short to ground.
11 FB I Feedback input for output voltage regulation. Connect a resistor divider to set the output voltage. Never short this pin to ground during operation.
12–15,
27–30		 NC — No internal connection. Connect to ground net and copper to improve heat sinking and board-level reliability.
16 PGOOD O Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = LOW when EN = low and VIN > 2 V.
17 SYNC/MODE I Synchronization input and mode setting pin. Do not float. Tie to ground if not used.
  • Tie to ground: auto mode, higher efficiency at light loads.
  • Tie to logic high: forced PWM, constant switching frequency over load.
  • Tie to external clock source: forced PWM, synchronize to the rising edge of the external clock.
18 EN I Enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to PVIN. Precision enable input allows adjustable input voltage UVLO using external resistor divider.
19 AGND GND Analog ground. Ground reference for internal circuitry. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB.
20–22 PVIN P Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors CIN. CIN must be placed right next to this pin and PGND pins on PCB, and connected with short and wide traces.
23–26 PGND GND Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP, AGND, ground side of CIN and COUT on PCB. Path to CIN must be as short as possible.
EP DAP GND Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation path for the device. Must be used for heat sinking by soldering to ground copper on PCB. Thermal vias are preferred to improve heat dissipation to other layers.
(1) A = analog, I = input, O = output, P = power, GND = ground
Table 5-2 Bare Die Information
DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS
7.52 mils Silicon with backgrind GND MetDCu 574.5 nm
Figure 5-2 TPS7H4010-SEP Bare Die Diagram
Table 5-3 Bond Pad Coordinates in Microns
DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX
NC 1 105.175 4204.585 235.375 4334.785
SW 2 105.175 3917.305 235.375 4047.505
SW 3 105.175 3630.025 235.375 3760.225
SW 4 105.175 3342.745 235.375 3472.945
SW 5 105.175 3055.465 235.375 3185.665
SW 6 105.175 2768.185 235.375 2898.385
SW 7 76.79 2352.945 206.99 2483.145
SW 8 76.79 2090.795 206.99 2220.995
SW 9 76.79 1828.645 206.99 1958.845
SW 10 76.79 1566.495 206.99 1696.695
CBOOT 11 74.375 1214.15 204.575 1344.35
PVCC 12 65.24 1006.81 195.44 1137.01
VCC 13 67.025 787.99 197.225 918.19
BIAS 14 67.025 595.56 197.225 725.76
RT 15 67.025 385.595 197.225 515.795
SS 16 67.025 211.435 197.225 341.635
FB 17 334.25 64.365 464.45 194.565
PGOOD 18 1511.79 227.185 1641.99 357.385
SYNC 19 1511.79 465.08 1641.99 595.28
EN 20 1511.79 673.54 1641.99 803.74
AGND 21 1497.72 881.895 1627.92 1012.095
AVIN 22 1497.72 1064.91 1627.92 1195.11
PVIN 23 1428.07 1566.495 1558.27 1696.695
PVIN 24 1428.07 1828.645 1558.27 1958.845
PVIN 25 1428.07 2090.795 1558.27 2220.995
PVIN 26 1428.07 2352.945 1558.27 2483.145
PGND 27 1535.835 2768.185 1666.035 2898.385
PGND 28 1535.835 3055.465 1666.035 3185.665
PGND 29 1535.835 3342.745 1666.035 3472.945
PGND 30 1535.835 3630.025 1666.035 3760.225
PGND 31 1535.835 3917.305 1666.035 4047.505
PGND 32 1535.835 4204.585 1666.035 4334.785