SNVSBL0A November   2020  – December 2021 TPS7H4010-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Synchronous Step-Down Regulator
      2. 7.3.2  Auto Mode and FPWM Mode
      3. 7.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 7.3.4  Adjustable Output Voltage
      5. 7.3.5  Enable and UVLO
      6. 7.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 7.3.7  Soft Start and Voltage Tracking
      8. 7.3.8  Adjustable Switching Frequency
      9. 7.3.9  Frequency Synchronization and Mode Setting
      10. 7.3.10 Internal Compensation and CFF
      11. 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 7.3.12 Power-Good and Overvoltage Protection
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 DCM Mode
        3. 7.4.3.3 PFM Mode
        4. 7.4.3.4 Fault Protection Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setpoint
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Input Capacitors
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-Forward Capacitor
        7. 8.2.2.7  Bootstrap Capacitors
        8. 8.2.2.8  VCC Capacitor
        9. 8.2.2.9  BIAS
        10. 8.2.2.10 Soft Start
        11. 8.2.2.11 Undervoltage Lockout Setpoint
        12. 8.2.2.12 PGOOD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout For EMI Reduction
      2. 10.1.2 Ground Plane
      3. 10.1.3 Optimize Thermal Performance
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNP|30
  • KGD|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 Adjustable Switching Frequency

The internal oscillator frequency is controlled by the impedance on the RT pin. If the RT pin is open circuit, the TPS7H4010-SEP operates at its default switching frequency, 500 kHz. The RT pin is not designed to be connected directly to ground. To program the switching frequency by RT resistor, either Equation 13, Figure 7-12, or Table 7-1 can be used to find the resistance value.

Equation 13. GUID-2AFAB090-19F3-4103-B685-17CBF46A67DA-low.gif
GUID-03885B09-245B-4A84-8E11-25F0C777D91B-low.gifFigure 7-12 RT Resistance vs Switching Frequency
Table 7-1 Typical Frequency Setting Resistance
SWITCHING FREQUENCY fSW (kHz) RT RESISTANCE (kΩ)
350 115
400 100
500 78.7 (or open)
750 52.3
1000 39.2
1500 26.1
2000 19.1
2200 17.4

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the solution. Lower switching frequency has lower switching losses (including gate charge losses, switch transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows the use of smaller power inductor and output capacitors, hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and has lower DCR. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. Factors that need to be taken into account include input voltage range, output voltage, most frequent load current level or levels, external component choices, solution size/cost requirements, efficiency, and thermal management requirements.

The choice of switching frequency may also be limited whether an operating condition triggers tON-MIN or tOFF-MIN. Minimum on-time, tON-MIN, is the smallest time that the HS switch can be on. Minimum off-time, tOFF-MIN, is the smallest duration that the HS switch can be off.

In CCM operation, tON-MIN and tOFF_MIN limits the voltage conversion range given a selected switching frequency, fSW. The minimum duty cycle allowed is:

Equation 14. DMIN = tON-MIN × fSW

The maximum duty cycle allowed is:

Equation 15. DMAX = 1 – tOFF-MIN × fSW

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operational supply voltage can be found by:

Equation 16. VIN_MAX = VOUT / (fSW × tON-MIN)

At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without frequency foldback can be approximated by:

Equation 17. VIN_MIN = VOUT / (1 – fSW × tOFF-MIN)

With a desired VOUT, the range of allowed VIN is narrower with higher switching frequency.

TPS7H4010-SEP has an advanced frequency fold-back algorithm under both tON_MIN and tOFF_MIN conditions. With frequency foldback, stable output voltage regulation is extended to wider range of supply voltages.

At very high VIN conditions, where tON-MIN limitation is met, the switching frequency reduces to allow higher VIN while maintaining VOUT regulation. Note that the peak to peak inductor current ripple will increase with higher VIN and lower frequency. TI does not recommend designing the circuit to operate with tON_MIN under typical conditions.

At very low VIN conditions, where tOFF-MIN limitation is met, the switching frequency decreases until tON-MAX condition is met. Such frequency foldback mechanism allows the TPS7H4010-SEP to have very low dropout voltage regardless of frequency setting.