SNVSCX9 October   2026 TPS7H4203-SEP

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power VIN Pins (PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Setting VOUT
        1. 8.3.3.1 Pulse-Width Limitations
          1. 8.3.3.1.1 Minimum Output Voltage
          2. 8.3.3.1.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Power Good (PWRGD)
      6. 8.3.6  Adjustable Switching Frequency and Synchronization
        1. 8.3.6.1 Internal Clock Mode
        2. 8.3.6.2 External Clock Mode
        3. 8.3.6.3 Internal Clock: Primary-Secondary
        4. 8.3.6.4 Clock Switchover
      7. 8.3.7  Switching Frequency Foldback
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Pulse Skipping During Start-up
        2. 8.3.8.2 Soft-Start (SS_TR)
        3. 8.3.8.3 Safe Start-Up Into Prebiased Outputs
        4. 8.3.8.4 Tracking and Sequencing
          1. 8.3.8.4.1 Sequential Start-Up Using EN and PWRGD
          2. 8.3.8.4.2 Ratiometric Start-Up Using Connected SS_TR Pins
          3. 8.3.8.4.3 Ratiometric and Simultaneous Start-Up
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side Overcurrent Protection (IOC)
          2. 8.3.9.1.2 COMP Shutdown
          3. 8.3.9.1.3 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 SW to PGND Schottky Diode
      3. 9.2.3 Application Curves
      4. 9.2.4 Parallel Operation Compensation
        1. 9.2.4.1 Input and Output Capacitance Reduction
          1. 9.2.4.1.1 Input Capacitor Reduction
          2. 9.2.4.1.2 Output Capacitor Reduction
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Data Sheet

TPS7H4203-SP and TPS7H4203-SEP 10V to 38V Input 3A Radiation-Hardened Synchronous Buck Converter