SLVSF07 July   2021 TPS7H5001-SP

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. 7.3.8.1 Internal Oscillator Mode
        2. 7.3.8.2 External Synchronization Mode
        3. 7.3.8.3 Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistors
        3. 8.2.2.3  Dead Time
        4. 8.2.2.4  Leading Edge Blank Time
        5. 8.2.2.5  Soft-Start Capacitor
        6. 8.2.2.6  Transformer
        7. 8.2.2.7  Main Switching FETs
        8. 8.2.2.8  Synchronous Rectificier FETs
        9. 8.2.2.9  RCD Clamp
        10. 8.2.2.10 Output Inductor
        11. 8.2.2.11 Output Capacitance and Filter
        12. 8.2.2.12 Sense Resistor
        13. 8.2.2.13 Hiccup Capacitor
        14. 8.2.2.14 Frequency Compensation Components
        15. 8.2.2.15 Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)

The TPS7H5001-SP allows for the user to program two independent dead times, TDSP and TDPS, as shown in Figure 7-9. This allows for the dead times to be optimized by the user in order to prevent shoot-though between the primary and synchronous switches while attaining the best possible converter efficiency. The dead time TDPS between primary output (OUTA and OUTB) turn-off to synchronous rectifier (SRA and SRB) turn-on, can be programmed using a resistor from PS to AVSS. Likewise, the dead time TDSP between synchronous rectifier turn-off and primary output turn-on is set using a resistor from SP to AVSS. The equation for determining the values of RPS and RSP required for a desired dead time is shown in Equation 8.

Equation 8.

where:

  • DT is the desired dead time in ns
  • RPS and RSP are in kΩ

If the PS and SP pins are left floating, the dead time will be set to a minimum value of 8 ns (typical). When these pins are populated, it is recommended to use a minimum resistor value of 10 kΩ for RPS and RSP. The maximum resistor value to be used is 300 kΩ. As mentioned in Soft-Start (SS) and Synchronous Rectifier Outputs (SRA and SRB), the SRA and SRB outputs will be disabled during soft-start, so the dead time is observed only after this sequence is complete.

After OUTA or OUTB goes high, a leading edge blank time is implemented to remove any transient noise from the current sensing loop. Like the dead time, the leading edge blank time is programmable by placing an external resistor from LEB to AVSS.This pin cannot be left floating and a minimum resistor value of 10 kΩ is required from LEB to AVSS. The maximum resistor value that should be used is 300 kΩ. The equation for determining the value of RLEB for a desired leading edge blank time is shown in Equation 9.

Equation 9.

where:

  • LEB is the desired leading edge blank time in ns
  • RLEB is in kΩ

In Figure 7-9, the dead times and leading edge blank times are shown for the switching waveforms. This figure also illustrates the minimum on-time of the device, which is comprised of the programmed blank time TLEB and an internal logic delay td.

GUID-20210708-CA0I-VDDV-KMW1-KZB82PHKJT5M-low.png Figure 7-9 Outputs Timing Waveforms