SLVSF07 July   2021 TPS7H5001-SP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. Internal Oscillator Mode
        2. External Synchronization Mode
        3. Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  Output Voltage Programming Resistors
        3.  Dead Time
        4.  Leading Edge Blank Time
        5.  Soft-Start Capacitor
        6.  Transformer
        7.  Main Switching FETs
        8.  Synchronous Rectificier FETs
        9.  RCD Clamp
        10. Output Inductor
        11. Output Capacitance and Filter
        12. Sense Resistor
        13. Hiccup Capacitor
        14. Frequency Compensation Components
        15. Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enable and Undervoltage Lockout (UVLO)

There are several methods for enabling the TPS7H5001-SP through the EN pin. The pin can be tied directly to VLDO, which would allow for the device to be enabled as soon as the voltage on VLDO surpasses the rising edge voltage threshold of the EN pin. The pin can also be driven with an externally generated signal or a compatible PGOOD signal for instances in which sequencing is desired. Lastly, two resistors can be used to program the controller to enable when VIN surpasses a user determined threshold, as shown in Figure 7-1 . The two resistors are configured as a divider, with one between VIN and EN and the other between EN and AVSS.

GUID-20210708-CA0I-TWQ6-ZP9S-RLHT9LT7SBKM-low.png Figure 7-1 Enable Pin Configuration Using Two External Resistors

Using Equation 1, the user can calculate the value for RUVLO_TOP for a chosen value of RUVLO_BOT based on the desired maximum startup voltage for the device. With these selected resistors Equation 2 can be used to determine the minimum startup voltage.

Equation 1. GUID-E8C5E2E9-796A-44BD-9BE8-769B62A5D39C-low.gif
Equation 2. GUID-2F63EA5B-0769-4233-BAB4-E98B212B803A-low.gif

In the two-resistor configuration of Figure 7-1, the controller will also shut down due to undervoltage lockout when the input voltage falls below a particular threshold. This is due to the hysteresis of the EN pin. In order to determine the voltages at which shutdown is expected to occur, use Equation 3 and Equation 4.

Equation 3. GUID-8A38ED83-B577-4A89-8A82-7F1FE61F2374-low.gif
Equation 4. GUID-331D7777-5CE0-4493-9C55-266BB51395C6-low.gif

It is important to note that the user should take care when selecting the values for RUVLO_TOP and RUVLO_BOT. It is recommended to optimize the selection of these resistors for startup in order to ensure proper operation. The UVLO value must be approximately 75% or less of the input voltage in order to ensure that the device turns on as expected under all circumstances. Setting the UVLO any higher may cause issues with the turn-on of the device. Figure 7-2 shows the expected startup and UVLO voltages on a 12 V rail where the maximum startup voltage is 90% of the nominal input voltage. In this instance, turn-off will occur when the input voltage falls to between 75% and 67% of its nominal value.

GUID-20210708-CA0I-XNNM-HJGL-7FG8VWJP8BGL-low.png Figure 7-2 Startup and UVLO Values for Two-Resistor Configuration with VIN = 12 V