SLVSF07 July   2021 TPS7H5001-SP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. Internal Oscillator Mode
        2. External Synchronization Mode
        3. Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  Output Voltage Programming Resistors
        3.  Dead Time
        4.  Leading Edge Blank Time
        5.  Soft-Start Capacitor
        6.  Transformer
        7.  Main Switching FETs
        8.  Synchronous Rectificier FETs
        9.  RCD Clamp
        10. Output Inductor
        11. Output Capacitance and Filter
        12. Sense Resistor
        13. Hiccup Capacitor
        14. Frequency Compensation Components
        15. Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Frequency Compensation

Since the TPS7H5001-SP uses a transconductance error amplifier (OTA), either Type 2A or Type 2B frequency compensation can be applied. The primary difference between the two compensation schemes is that Type 2A has an additional capacitor CHF in parallel with RCOMP and CCOMP in order to provide high-frequency noise attenuation. These components will be connected between the COMP pin of the controller, which is the OTA output, and AVSS.

GUID-20210113-CA0I-SRWS-DBGZ-G1WSBST3SWHZ-low.png Figure 7-13 TPS7H5001-SP Frequency Compensation Options

For any of the topologies supported by the TPS7H5001-SP, the following procedure and equations can be used to select the compensation components. All parameters in the equations are in standard units unless otherwise indicated (that is, H for inductance, F for capacitance, Hz for frequency, and so on).

  1. Select the desired crossover frequency (fc) for the converter.
  2. Calculate RCOMP based on the selected crossover frequency fc.

  1. Equation 19.


    • gmea is the error amplifier transconductance of 1800 × 10-6 A/V (typical)
    • VREF is the 0.613 V reference voltage (typical)
    • gmPS is the power stage transconductance (see Equation 23)

  2. Calculate CCOMP to place compensation zero at the location of the power stage dominant pole.
    Equation 20.
  3. Determine the output capacitor ESR zero location (optional).
    Equation 21.
  4. Select the capacitor CHF to provide a high frequency pole to compensate for the ESR zero (optional).
    Equation 22.

For different power converter topologies, the primary change to the compensation selection procedure will be the determination of the power stage transconductance gmPS. The power stage transconductance can be calculated as shown in Equation 23.

Equation 23.
  • NP is the number of primary turns on the main power transformer (set to 1 if no transformer is used)
  • NS is the number of secondary turns on the main power transformer (set to 1 if no transformer is used)
  • NCSP is the number of primary turns on the current sense transformer (set to 1 if no transformer is used)
  • NCSS is the number of secondary turns of the current sense transformer (set to 1 if no transformer is used)
  • RCS is the selected value of the current sense resistor
  • CCSR is the ratio to COMP of CS_ILIM

Note that for the TPS7H5001-SP, the sensed current waveform is compared to the voltage at COMP divided down by the factor CCSR at the PWM comparator, which is accounted for in the denominator of the equation. For buck converters, all turns for the main power transformer can be set equal to 1 and the equation still applies.