SLVSF07 July   2021 TPS7H5001-SP

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. 7.3.8.1 Internal Oscillator Mode
        2. 7.3.8.2 External Synchronization Mode
        3. 7.3.8.3 Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistors
        3. 8.2.2.3  Dead Time
        4. 8.2.2.4  Leading Edge Blank Time
        5. 8.2.2.5  Soft-Start Capacitor
        6. 8.2.2.6  Transformer
        7. 8.2.2.7  Main Switching FETs
        8. 8.2.2.8  Synchronous Rectificier FETs
        9. 8.2.2.9  RCD Clamp
        10. 8.2.2.10 Output Inductor
        11. 8.2.2.11 Output Capacitance and Filter
        12. 8.2.2.12 Sense Resistor
        13. 8.2.2.13 Hiccup Capacitor
        14. 8.2.2.14 Frequency Compensation Components
        15. 8.2.2.15 Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Hiccup Mode Operation (HICC)

Once the voltage at CS_ILIM exceeds 1.05 V, the device will execute cycle-by-cycle current limiting. The controller output is turned on at the beginning of each cycle until such point that CS_ILIM voltage reaches the current sense threshold VCS_ILIM, when the output is turned off. At the same time, each time the voltage at CS_ILIM reaches 1.05 V, the capacitor at CHICC is charged via a 80-µA current (hiccup delay current). This hiccup delay current is terminated at the end of the clock cycle. As long as there is still an overcurrent being detected, the cycle-by-cycle limiting will continue until the voltage on CHICC reaches 0.6 V. This cycle-by-cycle limiting period is referred to as the delay mode. As such, the capacitor CHICC can be chosen to dictate the amount of time that the controller will spend in delay mode.

Equation 13.

Note that this equation is an approximation since:

  • depending on the system behavior and if CHICC has been charged previously, CHICC may not start at 0 V as assumed by the equation
  • the 80-μA charging current is a pulsed current, the duration of which will be dictated by the nature of the overcurrent (that is,. when the current sense threshold is reached during each clock cycle)

After the voltage on HICC pin reaches 0.6 V, the SS pin of the controller is discharged and switching stops. The voltage on HICC is then quickly pulled up to 1 V with the pull-up current limited to approximately 1 mA. Once HICC voltage reaches 1 V, the 1-µA hiccup restart current begins to discharge CHICC. The controller will not switch until HICC voltage falls to 0.3 V. Once the voltage falls to 0.3 V, the controller will initiate its soft-start sequence again. If the overcurrent has disappeared, normal operation will resume. The hiccup time, which is the entire non-switching period, can be calculated using Equation 14.

Equation 14.

In summary, the capacitor CHICC on the HICC pin controls the amount of time the controller spends performing cycle-by-cycle limiting before switching stops, and also controls the amount of time switching is disabled before re-start is attempted again. It is recommended to use a minimum of 3.3 nF for CHICC.

Figure 7-11 Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer