The TPS7H5005-SEP, TPS75006-SEP, and TPS7H5007-SEP each have a configurable maximum duty cycle using the DCL pin. The TPS7H5008-SEP only supports 50% maximum duty cycle and the DCL pin must be connected to AVSS. Table 8-5 below shows the allowable maximum duty cycle limits for each device.
|DEVICE||DUTY CYCLE LIMIT OPTIONS|
|TPS7H5005-SEP||50%, 75%, 100%|
For applications in which 100% duty cycle is needed, the user should select one of the three compatible devices and connect DCL to VLDO. For other applications which require a duty cycle limit restriction, the DCL pin could be connected to AVSS for 50% duty cycle limit or left floating for 75% maximum duty cycle. Note that only TPS7H5005-SEP and TPS7H5008-SEP support the 50% duty cycle limit (DCL = AVSS), and OUTB/SRB are only active in this configuration. The 50% duty cycle limit case is intended to support applications such as the push-pull that require two primary switching outputs, and in the case of the TPS7H5005-SEP, two synchronous rectification outputs. If the controller is being operated in external synchronization mode, the most precise duty cycle limiting results are obtained when the applied system clock has a 50% duty cycle. Specifically, for the case when the duty cycle limit is set to 75% (DCL = floating) in the supported devices, there may be some variation of the duty cycle limit that is dependent on the duty cycle of the external clock applied at SYNC
|MAXIMUM DUTY CYCLE (NOMINAL)||DCL CONNECTION|