SLVSGG1A February   2022  – September 2022 TPS7H5005-SEP , TPS7H5006-SEP , TPS7H5007-SEP , TPS7H5008-SEP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: All Devices
    6. 7.6  Electrical Characteristics: TPS7H5005-SEP
    7. 7.7  Electrical Characteristics: TPS7H5006-SEP
    8. 7.8  Electrical Characteristics: TPS7H5007-SEP
    9. 7.9  Electrical Characteristics: TPS7H5008-SEP
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and VLDO
      2. 8.3.2  Start-Up
      3. 8.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Output Voltage Programming
      7. 8.3.7  Soft Start (SS)
      8. 8.3.8  Switching Frequency and External Synchronization
        1. Internal Oscillator Mode
        2. External Synchronization Mode
        3. Primary-Secondary Mode
      9. 8.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 8.3.10 Synchronous Rectifier Outputs (SRA/SRB)
      11. 8.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 8.3.12 Pulse Skipping
      13. 8.3.13 Duty Cycle Programmability
      14. 8.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 8.3.15 Hiccup Mode Operation (HICC)
      16. 8.3.16 External Fault Protection (FAULT)
      17. 8.3.17 Slope Compensation (RSC)
      18. 8.3.18 Frequency Compensation
      19. 8.3.19 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  Output Voltage Programming Resistors
        3.  Dead Time
        4.  Leading Edge Blank Time
        5.  Soft-Start Capacitor
        6.  Transformer
        7.  Main Switching FETs
        8.  Synchronous Rectificier FETs
        9.  RCD Clamp
        10. Output Inductor
        11. Output Capacitance and Filter
        12. Sense Resistor
        13. Hiccup Capacitor
        14. Frequency Compensation Components
        15. Slope Compensation Resistor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Primary-Secondary Mode

Two TPS7H500x-SEP controllers can be operated in a primary-secondary mode by utilizing the SYNC pin. As mentioned in Internal Oscillator Mode, when RT is selected to provide the desired switching frequency, SYNC outputs a clock signal at twice the switching frequency. As such, the clock input generated by the primary device could be used as the clock input at SYNC for the secondary controller, which would operate in external synchronization mode. This means that the RT pin of the primary device should be populated while the corresponding pin of the secondary device would be left floating.

The primary-secondary mode would be useful in a couple of scenarios. The first is for two independent converters that need to be synchronized to the same switching frequency. In this instance, the converters can be two converters can have different operating conditions or topologies. Besides the shared SYNC signal, there are no connections between the two converters.

Figure 8-10 Primary-Secondary Mode Configuration for Two Independent Converters

In a second scenario, two controllers can be used to design a single interleaved converter with phases in parallel. In this design, the VSENSE, COMP, SS, and HICC pins would need to be connected in addition to the shared SYNC connection.

Figure 8-11 Primary-Secondary Mode Configuration for Parallel Operation

When using two controllers in primary-secondary mode, it is important to note that secondary controller will invert the clock signal that it receives from the primary controller. As such, there will be phase shift between the switching outputs of the primary and secondary controllers. This phase shift from an output (i.e. OUTA) on the primary controller to the corresponding output on the secondary controller will be 90° or 270°, depending on when the secondary device synchronizes to its clock input. Note that in Figure 8-12, the waveforms for OUTB are only applicable for TPS7H5005-SEP and TPS7H5008-SEP.

Figure 8-12 Switching Waveforms for Primary-Secondary Mode

The three operational modes for the controller are summarized in Table 8-1.

Table 8-1 Oscillator Modes and Configurations
Internal oscillatorPopulated with resistor to AVSS.Configured as output. Generates in-phase clock at twice the switching frequency.Configurable from 100 kHz to 2 MHz depending on RT value.
External synchronizationFloating. Configured as input. Accepts 200-kHz to 4-MHz external clock that is inverted internally.Synchronized to SYNC input clock at ½ of the clock frequency. Switching is out-of-phase with external clock.
Primary-secondaryPopulated with resistor to AVSS on primary device. Floating on secondary device.Configured as output on primary device. Configured as input on secondary device. The SYNC pins of primary and secondary devices are connected.Configurable from 100 kHz to 2 MHz depending on RT value of primary device. Secondary device switching is either 90° or 270° out-of-phase with primary device.