SLUSD66D September   2019  – February 2021 TPS92520-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck Converter Switching Operation
      2. 7.3.2  Switching Frequency and Adaptive On-Time Control
      3. 7.3.3  Minimum On-Time, Off-Time, and Inductor Ripple
      4. 7.3.4  LED Current Regulation and Error Amplifier
      5. 7.3.5  Start-up Sequence
      6. 7.3.6  Analog Dimming and Forced Continuous Conduction Mode
      7. 7.3.7  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      8. 7.3.8  Internal PWM Dimming
      9. 7.3.9  Shunt FET Dimming or Matrix Beam Application
      10. 7.3.10 Bias Supply
      11. 7.3.11 Bootstrap Supply
      12. 7.3.12 ADC
        1. 7.3.12.1 Input Voltage Measurement: VINx
        2. 7.3.12.2 LED Voltage Measurement: CSNx
        3. 7.3.12.3 Bias Supply Measurement: V5D
        4. 7.3.12.4 External Limp-Home Input Measurement: LHI
        5. 7.3.12.5 Junction Temperature Measurement: TEMP
      13. 7.3.13 Faults and Diagnostics
      14. 7.3.14 Output Short Circuit Fault
      15. 7.3.15 Output Open Circuit Fault
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power On Reset (POR)
      2. 7.4.2 Detect SPI Communication
      3. 7.4.3 Standalone Mode
      4. 7.4.4 Load Mode
      5. 7.4.5 Run Mode
      6. 7.4.6 Sleep Mode
      7. 7.4.7 Limp-Home Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Command Frame
      3. 7.5.3 Response Frame
        1. 7.5.3.1 Read Response Frame Format
        2. 7.5.3.2 Write Response Frame Format
        3. 7.5.3.3 Write Error/POR Frame Format
      4. 7.5.4 SPI Error
      5. 7.5.5 SPI for Multiple Slave Devices in Parallel Configuration
      6. 7.5.6 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
        1. 7.6.1.1 SYSCFG1 Register (address = 0x00) [reset = 0x10]
        2. 7.6.1.2 SYSCFG2 Register (address = 0x01) [reset = 0x00]
        3. 7.6.1.3 CMWTAP Register (address = 0x02) [reset = 0x08]
      2. 7.6.2 STATUS Registers
        1. 7.6.2.1 STATUS1 Register (address = 0x03)
        2. 7.6.2.2 STATUS2 Register (address = 0x04)
        3. 7.6.2.3 STATUS3 Register (address = 0x05)
      3. 7.6.3 Device Control Registers
        1. 7.6.3.1  Thermal Warning Limit (address = 0x06) [reset = 0x8A]
        2. 7.6.3.2  SLEEP Command (address = 0x07) [reset = 0x00]
        3. 7.6.3.3  CH1IADJL Control Register (address = 0x08) [reset = 0x00]
        4. 7.6.3.4  CH1IADJH Control Register (address = 0x09) [reset = 0x00]
        5. 7.6.3.5  CH2IADJL Control Register (address = 0x0A) [reset = 0x00]
        6. 7.6.3.6  CH2IADJH Control Register (address = 0x0B) [reset = 0x00]
        7. 7.6.3.7  PWMDIV Register (address = 0x0C) [reset = 0x04]
        8. 7.6.3.8  CH1PWML Register (address = 0x0D) [reset = 0x00]
        9. 7.6.3.9  CH1PWMH Register (address = 0x0E) [reset = 0x00]
        10. 7.6.3.10 CH2PWML Register (address = 0x0F) [reset = 0x00]
        11. 7.6.3.11 CH2PWMH Register (address = 0x10) [reset = 0x00]
        12. 7.6.3.12 CH1TON Register (address = 0x11) [reset = 0x07]
        13. 7.6.3.13 CH2TON Register (address = 0x12) [reset = 0x07]
      4. 7.6.4 ADC Measurements
        1. 7.6.4.1  CH1VIN Measurement (address = 0x13)
        2. 7.6.4.2  CH1VLED Measurement (address = 0x14)
        3. 7.6.4.3  CH1VLEDON Measurement (address = 0x15)
        4. 7.6.4.4  CH1VLEDOFF Measurement (address = 0x16)
        5. 7.6.4.5  CH2VIN Measurement (address = 0x17)
        6. 7.6.4.6  CH2VLED Measurement (address = 0x18)
        7. 7.6.4.7  CH2VLEDON Measurement (address = 0x19)
        8. 7.6.4.8  CH2VLEDOFF Measurement (address = 0x1A)
        9. 7.6.4.9  TEMPL Measurement (address = 0x1B)
        10. 7.6.4.10 TEMPH Measurement (address = 0x1C)
        11. 7.6.4.11 V5D Measurement (address = 0x1D)
      5. 7.6.5 Limp-Home Configuration and Command Registers
        1. 7.6.5.1  LHCFG1 Register (address = 0x1E) [reset =0x00]
        2. 7.6.5.2  LHCFG2 Register (address = 0x1F) [reset =0x00h]
        3. 7.6.5.3  LHIL Measurement (address = 0x20)
        4. 7.6.5.4  LHIH Measurement (address = 0x21)
        5. 7.6.5.5  LHIFILTL Register (address = 0x22)
        6. 7.6.5.6  LHIFILTH Register (address = 0x23)
        7. 7.6.5.7  LH1IADJL Register (address = 0x24) [reset = 0x00]
        8. 7.6.5.8  LH1IADJH Register (address = 0x25) [reset = 0x00]
        9. 7.6.5.9  LH2IADJL Register (address = 0x26) [reset = 0x00]
        10. 7.6.5.10 LH2IADJH Register (address = 0x27) [reset = 0x00]
        11. 7.6.5.11 LH1PWML Register (address = 0x28) [reset = 0x00]
        12. 7.6.5.12 LH1PWMH Register (address = 0x29) [reset = 0x00]
        13. 7.6.5.13 LH2PWML Register (address = 0x2A) [reset = 0x00]
        14. 7.6.5.14 LH2PWMH Register (address = 0x2B) [reset = 0x00]
        15. 7.6.5.15 LH1TON Register (address = 0x2C) [reset = 0x07]
        16. 7.6.5.16 LH2TON Register (address = 0x2D) [reset = 0x07]
      6. 7.6.6 RESET Register (address = 0x2E) (Write-Only)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Consideration
      2. 8.1.2  Switching Frequency Selection
      3. 8.1.3  LED Current Set Point
      4. 8.1.4  Inductor Selection
      5. 8.1.5  Output Capacitor Selection
      6. 8.1.6  Input Capacitor Selection
      7. 8.1.7  Bootstrap Capacitor Selection
      8. 8.1.8  Compensation Capacitor Selection
      9. 8.1.9  Input Undervoltage Protection
      10. 8.1.10 CSN Protection Diode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Detailed Design Procedure
          1. 8.2.1.1.1 Calculating Duty Cycle
          2. 8.2.1.1.2 Calculating Minimum On-Time and Off-Time
          3. 8.2.1.1.3 Minimum Switching Frequency
          4. 8.2.1.1.4 LED Current Set Point
          5. 8.2.1.1.5 Inductor Selection
          6. 8.2.1.1.6 Output Capacitor Selection
          7. 8.2.1.1.7 Bootstrap Capacitor Selection
          8. 8.2.1.1.8 Compensation Capacitor Selection
          9. 8.2.1.1.9 External Channel Enable and PWM dimming
      2. 8.2.2 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Initialize Device without Watchdog timer
      2. 8.3.2 Initialize Device with Watchdog Timer
      3. 8.3.3 Limp-Home Mode
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
        1. 10.1.1.1 Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

-40°C ≤ TJ ≤ 150°C, V5D = V5A = 5 V, VIN = 24 V, VUDIMx = 5 V, CV5D =CV5A = 4.7 µF CBSTx = 0.1 µF, CCOMPx = 1 nF, RCSx = 100 mΩ, no load on SWx, LHI pin floating (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL ANALOG AND GATE DRIVE SUPPLIES (V5D, V5A)
VV5D,A(UVLO) V5D and V5A UVLO threshold Rising 4.10 4.26 V
Falling 3.84 4.00 V
Hysteresis 100 mV
IV5A(STBY) Analog supply stand-by current VUDIM1 = VUDIM2 = 0 V 4 5 mA
IV5D(STBY) Gate drive supply stand-by current VUDIM1 = VUDIM2 = 0 V 0.9 1.3 mA
IV5A(SLEEP) Analog supply sleep state current 16 300 nA
IV5D(SLEEP) Gate drive supply sleep state current 17 24 µA
IVINx(SLEEP) VIN pin sleep state current VINx = 15 V 2 4 μA
IV5D(SW) Gate drive supply switching current VV5D = 5 V, fSW = 1 MHz,  CH1 and CH2 switching 12 20 mA
HIGH-SIDE FET (SWx, BOOTx)
RDSx(ON-HS) High-side MOSFET on resistance VINx = 6 V, VBSTx = 11 V, IHSx = 100 mA 227 440 mΩ
VBSTx(UV) Bootstrap UVLO threshold Falling, VINx = 6 V, VSWx = 0 V 2.60 2.95 3.30 V
Hysteresis, VINx = 6 V, VSWx = 0 V 120 184 250 mV
IQ(xBST) Bootstrap pin quiescent current VBSTx = 5 V, VSWx = 0 V 200 250 300 µA
LOW-SIDE FET (SWx)
RDSx(ON-LS) Low-side MOSFET on resistance VINx = 6 V, ILSx = 100 mA 227 440 mΩ
HIGH-SIDE FET CURRENT LIMIT
IHSx(ILIM) High-side current limit threshold VINx = 6 V 2.1 2.7 3.5 A
tHSx(LEB) High-side current sense leading-edge blanking period VINx = 6 V 35 60 80 ns
tHSx(RES) Current limit response time VINx = 6 V 20 ns
LOW-SIDE FET CURRENT LIMIT
ILSx(ILIM) Low-side sinking current limit threshold VINx = 6 V 1.00 1.50 2.15 A
tLSx(LEB) Low-side current sense leading-edge blanking period VINx = 6 V 76 ns
OSCILLATOR
fOSC Oscillator frequency 9.2 10.8 12.4 MHz
ANALOG TO DIGITAL CONVERTER (VDD, VIN1, VIN2, VCSN1, VCSN2, LHI, TEMP)
tCONV ADC conversion time 18 µs
VADC(FS) ADC full scale 2.38 2.45 2.52 V
qADC ADC LSB 2.4 mV
ADCINL Integral nonlinearity –2 2 LSB
ADCDNL Differential nonlinearity –2 2 LSB
qTEMP Temperature LSB 1.4 count
ADCTEMP ADC measurement output TJ = 25 °C 414 count
TJ = 125 °C 553 count
KVINx VINx sense resistor divider ratio 0.037
KV5D V5D sense resistor divider ratio 0.45
KLHI LHI sense resistor divider ratio 1
ANALOG ADJUST SETTING AND CURRENT SENSE AMPLIFIER (CSPx, CSNx)
VDACx(FS) DAC full scale 2.38 2.45 2.52 V
qDAC DAC resolution 2.33 2.40 2.47 mV
DACxINL Integral nonlinearity –1 1 LSB
DACxDNL Differential nonlinearity CHxADJ stepped (63-64, 127-128, 255-256, 511-512, 1022-1023) –0.85 0.85 LSB
V(CSPx-CSNx) Current sense threshold VCSPx = 6 V,
ILED_REF_DACx = 1023		 167.5 173.0 178.5 mV
VCSPx = 6 V,
ILED_REF_DACx = 512		 83.0 88.5 94.0 mV
VCSPx = 6 V,
ILED_REF_DACx = 192		 29.0 34.5 40.0 mV
VCSPx = 6 V,
ILED_REF_DACx = 63		 6.5 12.5 18.5 mV
gmx(LV) Level shift amplifier transconductance VINx = 63 V, VCSNx = 5 V 50 µA/V
VCSPx(SHT) Output short circuit detection threshold Rising 2.65 V
Falling 2.45 V
VALLEY CURRENT COMPARATOR (CSPx, CSNx)
VVALx(OS) Systematic comparator offset voltage VCSNx < 2.4 V 17 mV
ON-TIME GENERATOR
tONx(MIN) Minimum on-time. VINx = 4.5 V 87 105 123 ns
tONx Programmed on-time VINx = 50 V, VCSPx = 38 V, tonx_DAC = 39 295 375 460 ns
VINx = 50 V, VCSPx = 25 V, tonx_DAC = 7 900 1155 1400 ns
OFF-TIME GENERATOR
tOFFx(MIN) Minimum off-time VINx = 4.5 V 44 57 68 ns
PWM DIMMING and PROGRAMMABLE UVLO INPUT (DIMx)
VUDIMx(EN) UDIM input threshold Rising 1.22 1.27 V
Falling 1.075 1.120 V
IUDIMx(UVLO) UDIM source current (UVLO hysteresis) VUDIMx = 1.5 V 8 10 12 µA
ERROR AMPLIFIER (COMPx)
gM Transconductance VINx = 63 V 450 µA/V
ICOMPx(SRC) COMPx current source capacity VINx = 63 V, V(CSPx–CSNx) = 0 V, CHxIADJ = 578 45 µA
ICOMPx(SINK) COMPx current sink capacity VINx = 63 V, V(CSPx–CSNx) = 200 mV, CHxIADJ = 578 45 µA
EAx(BW) Bandwidth Unity gain 3 MHz
EA(VD) Input differential sense range –225 225 mV
EA(CM) Input common mode range VINx = 63 V 0 VINx – 0.5 V
ICOMPx(LKG) COMPx leakage current VUDIMx = 0 V 2.5 nA
VCOMPx(ST) COMPx startup threshold Rising 2.45 V
Hysteresis 250 mV
VCOMPx(OV) COMPx over-voltage detection threshold Rising 3.0 3.2 V
Hysteresis 60 mV
RCOMPx(DCH) COMPx discharge FET resistance 230 Ω
VCOMPx(RST) Reset voltage Falling 100 mV
LIMP HOME CURRENT SET POINT (LHI)
ILHI Source current VIN = 6 V 8 10 12 µA
VLHI(SD) Shutdown threshold Rising, VIN = 6 V 174 200 227 mV
Falling, VIN = 6 V 119 148 176 mV
FAULT INDICATOR (FLT)
R(FLT) Fault pin pull-down resistance 3 7 Ω
TOC Hiccup retry delay time 3.6 ms
SERIAL PERIPHERAL INTERFACE (MOSI, MISO, SCK, SSN)
VOL-MISO Output low voltage threshold IMISO = 10 mA 0.5 V
RDS-MISO IMISO = 10 mA 50 Ω
VINPUT(RISE) Logic threshold (SSN, SCK, MOSI) Rising 1.8 V
VINPUT(FALL) Falling 0.8 V
tSS-SU SSN setup time Falling edge of SSN to 1st SCK rising edge 500 ns
tSS-H SSN hold time Falling edge of 16th SCK to SSN rising edge 250 ns
tSS-HI SSN high time Time SSN must remain high between transactions 1000 ns
tSCK SCK period Clock period 500 ns
DSCK SCK duty cycle Clock duty cycle 40 60 %
tSU MOSI setup time MOSI valid to rising edge SCK 125 ns
tH MOSI hold time MOSI valid after rising edge SCK 140 ns
tHI_Z MISO tri-state time Time to tri-state MISO after SSN rising edge 110 320 ns
tMISO_HL MISO valid high-to-low Time to place valid "0" on MISO after falling SCK edge 320 ns
tMISO_LH MISO valid low-to-high Time to tri-state MISO after falling SCK edge 320+tRC ns
tZO_HL MISO drive time high-to-low SSN Falling Edge to MISO falling 320 ns
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C
TSD(HYS) Thermal shutdown hysteresis 16 °C