SLUSCV5 May   2022 TPS92643-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal Regulator
      2. 7.3.2  Buck Converter Switching Operation
      3. 7.3.3  Bootstrap Supply
      4. 7.3.4  Switching Frequency and Adaptive On-Time Control
      5. 7.3.5  Minimum On-Time, Off-Time, and Inductor Ripple
      6. 7.3.6  LED Current Regulation and Error Amplifier
      7. 7.3.7  Start-Up Sequence
      8. 7.3.8  Analog Dimming and Forced Continuous Conduction Mode
      9. 7.3.9  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      10. 7.3.10 Analog Pulse Width Modulator Circuit
      11. 7.3.11 Output Short and Open-Circuit Faults
      12. 7.3.12 Overcurrent Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Fault Indicator and Diagnostics Summary
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Considerations
      2. 8.1.2  Switching Frequency Selection
      3. 8.1.3  LED Current Programming
      4. 8.1.4  Inductor Selection
      5. 8.1.5  Output Capacitor Selection
      6. 8.1.6  Input Capacitor Selection
      7. 8.1.7  Bootstrap Capacitor Selection
      8. 8.1.8  Bootstrap Resistor Selection
      9. 8.1.9  Compensation Capacitor Selection
      10. 8.1.10 Input Dropout and Undervoltage Protection
      11. 8.1.11 APWM Input and Thermal Protection
      12. 8.1.12 Protection Diodes
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Calculating Duty Cycle
        2. 8.2.2.2  Calculating Minimum On-Time and Off-Time
        3. 8.2.2.3  Minimum Switching Frequency
        4. 8.2.2.4  LED Current Set Point
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Bootstrap Resistor Selection
        9. 8.2.2.9  Compensation Capacitor Selection
        10. 8.2.2.10 VIN Dropout Protection and PWM Dimming
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
        1. 10.1.1.1 Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt from pulsing currents in switching converters. The larger the area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In buck converters, the pulsing current path is from the VIN side of the input capacitors through the HS switch, through the LS switch, and then returns to the ground of the input capacitor.

High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic capacitors as close as possible to the VIN and PGND pins is the key to EMI reduction.

The PCB copper connection of the SW pin to the inductor must be as short as possible and just wide enough to carry the LED current without excessive heating. Short, thick traces or, copper pours (shapes), must be used for high current conduction path to minimize parasitic resistance. Place the output capacitor close to the CSN pin and grounded closely to the PGND pin.