DLPS039F December 2015 – April 2019 TPS99000-Q1
The asynchronous internal reset of the device places system in this state. All supplies (DMD supplies, 1.1 V, 1.8 V, 3.3 V) are asynchronously disabled and RESETZ output to DLPC230-Q1 is held low. Once the internal reset is released, communication over SPI2 is supported.
Exit from OFF state progresses to the STANDBY state. To exit OFF state, the following must all be true:
Internal monitors of 1.1 V, 1.8 V, and 3.3 V (and 6 V input on VIN_LDOT_5V) will hold off progression to STANDBY until all 4 rails are in operational range. After power is good, RESETZ output signal is held low for a specific period to ensure a proper reset cycle for the DLPC230-Q1, and then it is released to transition to STANDBY.