DLPS039F December   2015  – April 2019 TPS99000-Q1


  1. Features
  2. Applications
  3. Description
    1.     Typical Standalone System
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions - Initialization, Clock, and Diagnostics
    2.     Pin Functions - Power and Ground
    3.     Pin Functions - Power Supply Management
    4.     Pin Functions - Illumination Control
    5.     Pin Functions - Serial Peripheral Interfaces
    6.     Pin Functions - Analog to Digital Converter
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Transimpedance Amplifier Parameters
    6. 6.6  Electrical Characteristics - Digital to Analog Converters
    7. 6.7  Electrical Characteristics - Analog to Digital Converter
    8. 6.8  Electrical Characteristics - FET Gate Drivers
    9. 6.9  Electrical Characteristics - Photo Comparator
    10. 6.10 Electrical Characteristics - Voltage Regulators
    11. 6.11 Electrical Characteristics - Temperature and Voltage Monitors
    12. 6.12 Electrical Characteristics - Current Consumption
    13. 6.13 Power-Up Timing Requirements
    14. 6.14 Power-Down Timing Requirements
    15. 6.15 Timing Requirements - Sequencer Clock
    16. 6.16 Timing Requirements - Host / Diagnostic Port SPI Interface
    17. 6.17 Timing Requirements - ADC Interface
    18. 6.18 Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Illumination Control
        1. Illumination System High Dynamic Range Dimming Overview
        2. Illumination Control Loop
        3. Continuous Mode Operation
          1. Output Capacitance in Continuous Mode
          2. Continuous Mode Driver Distortion and Blanking Current
          3. Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. Continuous Mode Constant OFF Time
          5. Continuous Mode Current Limit
        4. Discontinuous Mode Operation
          1. Discontinuous Mode Pulse Width Limit
          2. COMPOUT_LOW Timer in Discontinuous Operation
          3. Dimming Within Discontinuous Operation Range
          4. Multiple Pulse Heights to Increase Bit Depth
          5. TIA Gain Adjustment
          6. Current Limit in Discontinuous Mode
          7. CMODE Big Cap Mode in Discontinuous Operation
      2. 7.3.2 Over-Brightness Detection
        1. Photo Feedback Monitor BIST
        2. Excessive Brightness BIST
      3. 7.3.3 Analog to Digital Converter
        1. Analog to Digital Converter Input Table
      4. 7.3.4 Power Sequencing and Monitoring
        1. Power Monitoring
      5. 7.3.5 DMD Mirror Voltage Regulator
      6. 7.3.6 Low Dropout Regulators
      7. 7.3.7 System Monitoring Features
        1. Windowed Watchdog Circuits
        2. Die Temperature Monitors
        3. External Clock Ratio Monitor
      8. 7.3.8 Communication Ports
        1. Serial Peripheral Interface (SPI)
    4. 7.4 Device Functional Modes
      1. 7.4.1 OFF
      2. 7.4.2 STANDBY
      3. 7.4.3 POWERING_DMD
      4. 7.4.4 DISPLAY_RDY
      5. 7.4.5 DISPLAY_ON
      6. 7.4.6 PARKING
      7. 7.4.7 SHUTDOWN
    5. 7.5 Register Maps
      1. 7.5.1 System Status Registers
      2. 7.5.2 ADC Control
      3. 7.5.3 General Fault Status
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HUD
        1. Design Requirements
        2. Application Design Considerations
          1. Photodiode Considerations
          2. LED Current Measurement
          3. Setting the Current Limit
          4. Input Voltage Variation Impact
          5. Discontinuous Mode Photo Feedback Considerations
          6. Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
      2. 8.2.2 Headlight
        1. Design Requirements
  9. Power Supply Recommendations
    1. 9.1 TPS99000-Q1 Power Supply Architecture
    2. 9.2 TPS99000-Q1 Power Outputs
    3. 9.3 Power Supply Architecture
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power/High Current Signals
      2. 10.1.2 Sensitive Analog Signals
      3. 10.1.3 High Speed Digital Signals
      4. 10.1.4 High Power Current Loops
      5. 10.1.5 Kelvin Sensing Connections
      6. 10.1.6 Ground Separation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Tape and Reel Information
      2. 12.1.2 Mechanical Drawings

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Photodiode Considerations

Placement of the photodiode within the optical path is critical to system performance. Carefully optimizing the placement and electrical response of the photodiode will yield the widest dynamic range for dimming. Treatment of photodiode considerations are addressed in the Photodiode Selection and Placement Guide (DLPA082).

Several factors for the photodiode should be considered:

  • Position:
    • Ideally, a position in the illumination path (Figure 42) should be located that produces strong, but also balanced amplitude signal responses from each of the three LEDs at the system's target white point. Imbalance between the three channels due to non-ideal placement of the detector will limit dynamic range of the dimming system. The TIA supports an RGB trim function to help re-balance an imbalanced system. This feature is useful for completing the process of optimizing the balance of the amplitude signal responses from each LED. But it is still advisable to take care in the design of the illumination path such that the natural balance of the colors is as ideal as practical.
    • An additional consideration when determining position of photodiode is back scattered light from the projection path. Some amount of on state light will reflect backwards from the surfaces of the projection lens and other objects in the light path after the DMD. If the photodiode is placed in a position that is illuminated by this back scattered light, the photodiode will see a mixture of true illumination light plus this back scattered output light. If the back scattered light is significant, the illumination control loop will be impacted. Also, the back scatter is dependent on the video content (i.e. a solid white pattern may cause more back scatter than a solid black pattern), which impacts the full-on full-off contrast.
  • Irradiance on the Photodiode:
    • It is also important that the irradiance on the photodiode is not too high or too low. A high magnitude of irradiance can cause saturation and slower response from the photodiode. This varies depending on the specific photodiode selected for use. The TPS99000-Q1 provides a negative LDO and negative voltage source to provide a low noise –8 V reference for reverse biasing the photodiode. Reverse biasing the photodiode (photo conductive mode) increases the amount of irradiance the photodiode can accept without saturating as compared to a zero bias case (photovoltaic mode). On the other hand, a low magnitude of irradiance can make the system more susceptible to noise, including photodiode dark current. It is best to operate at photodiode current levels high enough so that dark current is negligible to avoid potential issues due to other noise sources (noise on cabling, grounding, etc).
  • Cable to remote PD placement:
    • If the photodiode is located remotely it is recommended to use a low capacitance cable and minimize the cable length. At a minimum: for noise rejection, use a one conductor shielded cable with the photodiode bias (cathode) connected to the cable shield and the photodiode output (anode) connected to the inner conductor. Better noise rejection is possible using shielded two conductor cables with the shield tied to a low noise ground. Experiments may be necessary to determine an optimal photodiode position to achieve adequate response balance between the colors and an acceptable irradiance level. Care must be taken to not exceed the maximum total photodiode capacitance (diode plus cable and connectors) as specified inElectrical Characteristics - Transimpedance Amplifier Parameters. TIA design includes adjustable feedback capacitance to optimize response for specific solutions. DLPC230-Q1 flash configuration options allow tuning of this feedback capacitance for optimal slew rate and stability performance.
TPS99000-Q1 photodiode_placement_DLPS039.gifFigure 42. Photodiode Placement

The photodiode conditioning circuits include several features to improve performance and integration:

  • Independent red, green and blue parameters for gain and offset
  • Selectable feedback capacitance
  • Integrated negative LDO, to provide photodiode reverse bias