DLPS039F December   2015  – April 2019 TPS99000-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical Standalone System
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions - Initialization, Clock, and Diagnostics
    2.     Pin Functions - Power and Ground
    3.     Pin Functions - Power Supply Management
    4.     Pin Functions - Illumination Control
    5.     Pin Functions - Serial Peripheral Interfaces
    6.     Pin Functions - Analog to Digital Converter
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Transimpedance Amplifier Parameters
    6. 6.6  Electrical Characteristics - Digital to Analog Converters
    7. 6.7  Electrical Characteristics - Analog to Digital Converter
    8. 6.8  Electrical Characteristics - FET Gate Drivers
    9. 6.9  Electrical Characteristics - Photo Comparator
    10. 6.10 Electrical Characteristics - Voltage Regulators
    11. 6.11 Electrical Characteristics - Temperature and Voltage Monitors
    12. 6.12 Electrical Characteristics - Current Consumption
    13. 6.13 Power-Up Timing Requirements
    14. 6.14 Power-Down Timing Requirements
    15. 6.15 Timing Requirements - Sequencer Clock
    16. 6.16 Timing Requirements - Host / Diagnostic Port SPI Interface
    17. 6.17 Timing Requirements - ADC Interface
    18. 6.18 Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Illumination Control
        1. 7.3.1.1 Illumination System High Dynamic Range Dimming Overview
        2. 7.3.1.2 Illumination Control Loop
        3. 7.3.1.3 Continuous Mode Operation
          1. 7.3.1.3.1 Output Capacitance in Continuous Mode
          2. 7.3.1.3.2 Continuous Mode Driver Distortion and Blanking Current
          3. 7.3.1.3.3 Continuous Mode S_EN2 Dissipative Load Shunt Options
          4. 7.3.1.3.4 Continuous Mode Constant OFF Time
          5. 7.3.1.3.5 Continuous Mode Current Limit
        4. 7.3.1.4 Discontinuous Mode Operation
          1. 7.3.1.4.1 Discontinuous Mode Pulse Width Limit
          2. 7.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
          3. 7.3.1.4.3 Dimming Within Discontinuous Operation Range
          4. 7.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
          5. 7.3.1.4.5 TIA Gain Adjustment
          6. 7.3.1.4.6 Current Limit in Discontinuous Mode
          7. 7.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
      2. 7.3.2 Over-Brightness Detection
        1. 7.3.2.1 Photo Feedback Monitor BIST
        2. 7.3.2.2 Excessive Brightness BIST
      3. 7.3.3 Analog to Digital Converter
        1. 7.3.3.1 Analog to Digital Converter Input Table
      4. 7.3.4 Power Sequencing and Monitoring
        1. 7.3.4.1 Power Monitoring
      5. 7.3.5 DMD Mirror Voltage Regulator
      6. 7.3.6 Low Dropout Regulators
      7. 7.3.7 System Monitoring Features
        1. 7.3.7.1 Windowed Watchdog Circuits
        2. 7.3.7.2 Die Temperature Monitors
        3. 7.3.7.3 External Clock Ratio Monitor
      8. 7.3.8 Communication Ports
        1. 7.3.8.1 Serial Peripheral Interface (SPI)
    4. 7.4 Device Functional Modes
      1. 7.4.1 OFF
      2. 7.4.2 STANDBY
      3. 7.4.3 POWERING_DMD
      4. 7.4.4 DISPLAY_RDY
      5. 7.4.5 DISPLAY_ON
      6. 7.4.6 PARKING
      7. 7.4.7 SHUTDOWN
    5. 7.5 Register Maps
      1. 7.5.1 System Status Registers
      2. 7.5.2 ADC Control
      3. 7.5.3 General Fault Status
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HUD
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Application Design Considerations
          1. 8.2.1.2.1 Photodiode Considerations
          2. 8.2.1.2.2 LED Current Measurement
          3. 8.2.1.2.3 Setting the Current Limit
          4. 8.2.1.2.4 Input Voltage Variation Impact
          5. 8.2.1.2.5 Discontinuous Mode Photo Feedback Considerations
          6. 8.2.1.2.6 Transimpedance Amplifiers (TIAs, Usage, Offset, Dark Current, Ranges, RGB Trim)
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
  9. Power Supply Recommendations
    1. 9.1 TPS99000-Q1 Power Supply Architecture
    2. 9.2 TPS99000-Q1 Power Outputs
    3. 9.3 Power Supply Architecture
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power/High Current Signals
      2. 10.1.2 Sensitive Analog Signals
      3. 10.1.3 High Speed Digital Signals
      4. 10.1.4 High Power Current Loops
      5. 10.1.5 Kelvin Sensing Connections
      6. 10.1.6 Ground Separation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Tape and Reel Information
      2. 12.1.2 Mechanical Drawings

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power-Down Timing Requirements(1)

MIN MAX UNIT
tvhold1 Host voltage hold time after VMAIN minimum threshold reached.
tmon4(max) + tpark(max) + tw2(max)
VMAIN threshold to 6 V and 3.3 V power loss.(2)(3) 900 μs
tvhold2 Host voltage hold time after PROJ_ON de-asserted.
tmon5(max) + tpark(max) + tw2(max)
VMAIN threshold to 6 V and 3.3 V power loss.(2)(3) 1.78 ms
tmon4 VMAIN monitoring time. Minimum voltage trip threshold to PARKZ falling edge. 52 120 μs
tmon5 PROJ_ON de-assertion reaction time. Falling edge of PROJ_ON to PARKZ falling edge. 1 ms
tpark DMD Park time. PARKZ falling edge to start DMD_VOFFSET discharge. 280 μs
tdischarge(4) DMD voltage rail discharge time. VOFFSET Cout= 1 μF
VRESET Cout= 1 μF
VBIAS Cout= 0.47 μF
260 μs
tw2 DMD voltage disable to RESETZ de-assertion. Start of DMD voltage rail discharge to RESETZ falling edge. 500 μs
There are two methods for initiating the power down sequence:
  1. VMAIN voltage decreases below its minimum threshold. This is typical if the TPS99000-Q1 is expected to initiate the power down sequence when main power is removed from the system. Note that the 6 V and 3.3 V input rails must remain within operating range for a specified period of time after the power-down sequence begins.
  2. PROJ_ON low. This is allows a host controller to initiate power down through a digital input to the TPS99000-Q1.
6 V input rails include DRVR_PWR, VIN_DRST, VIN_LDOT_5V, VIN_LDOA_3P3V, VIN_LDOT3P3V.
3.3 V input rails include VDD_IO, DVDD, AVDD.
The DMD specifies a maximum absolute voltage difference between VBIAS and VOFFSET. In order to remain below this maximum voltage difference, VBIAS must discharge faster than VOFFSET. This is accomplished by using a smaller Cout capacitance for VBIAS in order to allow it to discharge quicker than VOFFSET.
TPS99000-Q1 time_pwr_down_pwrloss.gifFigure 2. Power Down Timing - VMAIN Trigger
TPS99000-Q1 time_pwr_down_projon_v2.gifFigure 3. Power Down Timing - PROJ_ON Trigger