SNVSCB9A march   2023  – april 2023 TPSF12C1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active EMI Filtering
        1. 8.3.1.1 Schematics
      2. 8.3.2 Capacitive Amplification
      3. 8.3.3 Integrated Line Rejection Filter
      4. 8.3.4 Compensation
      5. 8.3.5 Remote Enable
      6. 8.3.6 Supply Voltage UVLO Protection
      7. 8.3.7 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – AEF Circuit for a High-Density 3-kW Server Rack Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sense Capacitors
          2. 9.2.1.2.2 Inject Capacitor
          3. 9.2.1.2.3 Compensation Network
          4. 9.2.1.2.4 Injection Network
          5. 9.2.1.2.5 Surge Protection
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Injection Network

The components connected between the INJ pin and inject capacitor establish a damped injection network. Damping is specifically required to manage resonance between the CM choke inductance and inject capacitance, which manifests in the AEF loop gain as a pair of complex zeros.

Figure 9-3 highlights three specific RC branches: RD1, RD1A and CD1 form one branch from the INJ pin; RD2 and CD2 in series connect to GND; RD3 and CD3 in parallel connect to the inject capacitor.

GUID-20221108-SS0I-8R7L-RHGC-XMD9G1DFHPMK-low.svg Figure 9-3 Injection Network

Based on the injection mechanism, the AEF circuit presents a low shunt impedance to CM noise. Given the three damping impedance branches highlighted in Figure 9-3, Equation 1 approximates the AEF impedance as:

Equation 1. GUID-20221107-SS0I-TCBD-4BLV-QBHHCKLKWWSQ-low.svg

where the term GAEF is the gain from the power lines to the INJ node (see the TPSF12C1 quickstart calculator for related detail).

Equation 1 shows that the impedance ZINJ appears in series with ZD3 and a parallel combination of ZD1 and ZD2. Furthermore, the gain GAEF is reduced by the voltage divider ratio between ZD2 and ZD1. These effects combine to increase the effective impedance of the AEF and hence reduce its attenuation performance, thus illustrating a trade-off between performance and stability.

So while an injection network is needed for stability, it also adds impedance in series with the inject capacitor, thus compromising EMI mitigation. As shown below, the user can minimize the impact on performance with careful and appropriate design.

GUID-20221109-SS0I-8N5B-JB1T-6ZT39CKVG40L-low.svg Figure 9-4 Dominant Components of the Injection Network vs Frequency

Illustrated in Figure 9-4, at low frequencies in the range of 5 kHz to 50 kHz, components RD1 and CD2 provide compensation and RD3 damps the effects of LC resonance. At higher frequencies (above 10 kHz), the dominant component impedance of each branch transitions to enable better attenuation performance:

  • RD1 transitions to CD1
  • CD2 transitions to RD2
  • RD3 transitions to CD3

Finally, CD1 transitions to RD1A if needed for phase margin of the AEF loop at high frequencies, typically above 100 kHz. When viewed in a clockwise direction, Figure 9-4 shows these transitions in sequence as frequency increases.

Below are basic guidelines to select the component values for the injection network:

  1. The undamped loop gain characteristic is likely to be unstable within the range of 5 kHz to 50 kHz, which, as mentioned previously, relates to an LC resonance between CM choke inductance and inject capacitance. Observe from circuit simulation – or by using the TPSF12C1 quickstart calculator – the frequency, fLFstability, at which the phase crosses –180° with positive gain, indicating negative gain margin.
  2. Choose a corner frequency with RD1 and CD2 equal to one fifth of the instability frequency:
    Equation 2. GUID-20221107-SS0I-BFQS-MNSM-B0ZPBSLP4KWC-low.svg
    Assigning RD1 = 1 kΩ and assuming instablity at 35 kHz, use Equation 3 to find a value for the capacitance of CD2:
    Equation 3. GUID-20221107-SS0I-3JMX-SF0V-0JCWZTKNW8VQ-low.svg
  3. Select CD1 < CD2, where a typical choice is CD1 = CD2/5 = 4.7 nF.
  4. Choose the resistance of RD2 such that the RD2, CD2 corner frequency is equal to that of RD1, CD1:
    Equation 4. GUID-20221107-SS0I-9R8D-K7WL-BQVDCHDSQDKJ-low.svg
  5. Select the resistance of RD3 to damp the resonance around the instability frequency, fLFstability.
    • A typical choice for RD3 is 500 Ω to 1 kΩ.
    • Assign CD3 equal to CINJ or a suitable value such that the RD3, CD3 corner frequency is less than switching frequency.
    • A lower resistance for RD3 results in more damping but at the penalty of reduced high-frequency attenuation (or forces a higher value for CD3 to maintain the applicable corner frequency below the switching frequency).
  6. Select a resistance for RD1A of 50 Ω to improve the phase margin of the AEF loop (if needed).