SLVSFR3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Design Procedure - Chassis Ground Reference

GUID-20220203-SS0I-5RSG-PFZF-WB3FXDTPWRN7-low.svg Figure 9-11 Chassis Ground Reference

RISO1 Selection

In order to protect the TPSI2140-Q1, RISO1 must be sized to limit the current in an overvoltage condition. The amount of resistance required to protect the TPSI2140-Q1 depends on the amount of overvoltage applied. For example, during a dielectric withstand voltage test (HiPot) of 3500 V for 5 seconds, the S1 to S2 voltage will be clamped to 1300 V (VAVA minimum) by the TPSI2140-Q1 and the RISO1 resistance required to keep the current under 2 mA would be 1.1 MΩ.

Equation 7. I A V A = V H I P O T - V A V A R I S O 1 = 3500 V - 1300 V 1.1   M Ω = 2 . 0 m A

If the high potential test lasts for 60 seconds, the RISO1 resistance must be doubled to 2.2 MΩ to keep the current below 1 mA.

DC Overvoltage

RISO1 Minimum (5 second intervals)

RISO1 Minimum (60 second intervals)

2000 V

350 kΩ

700 kΩ

2500 V

600 kΩ

1200 kΩ

3500 V

1100 kΩ

2200 kΩ

4300 V

1500 kΩ

3000 MΩ