SLUSEP8 January   2022 TPSM5D1806E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (VIN = 12 V)
    7. 6.7 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Output Voltage
      2. 7.3.2  Frequency Selection
        1. 7.3.2.1 Synchronization
        2. 7.3.2.2 Allowable Switching Frequency
      3. 7.3.3  Minimum and Maximum Input Voltage
      4. 7.3.4  Recommended Settings
      5. 7.3.5  Device Mode Configuration
        1. 7.3.5.1 MODE1 (Operating Mode and Phase Position)
        2. 7.3.5.2 MODE2 (Setting the Switching Frequency)
      6. 7.3.6  Input Capacitors
      7. 7.3.7  Minimum Required Output Capacitance
      8. 7.3.8  Ambient Temperature Versus Total Power Dissipation
      9. 7.3.9  Remote Sense
      10. 7.3.10 Enable (EN) and Undervoltage Lockout (UVLO)
      11. 7.3.11 Soft Start
      12. 7.3.12 Power Good
      13. 7.3.13 Safe Start-Up into Pre-Biased Outputs
      14. 7.3.14 BP5
      15. 7.3.15 Overcurrent Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application (Dual Outputs)
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Capacitor Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application (Paralleled Outputs)
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1 Output Voltage Setpoint
          2. 8.2.4.2.2 Input Capacitors
          3. 8.2.4.2.3 Output Capacitor Selection
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Package Specifications
      2. 10.2.2 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over TA = –55°C to +125°C, VIN = 12 V (unless otherwise noted);  Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VIN Operating input voltage range 4.5(1) 15 V
UVLO VIN turn on VIN increasing 3.5 3.7 3.9 V
Hysteresis 200 mV
IQ Quiescent current Non-switching, VFB1, VFB2 > 0.5 V, TA = 25°C, EN1 = EN2 = 5 V 4 mA
ISHDN Shutdown supply current TA = 25°C, EN1 = EN2 = 0 V 270 µA
INTERNAL LDO (BP5)
BP5 Regulation voltage 6 V ≤ VIN ≤ 15 V, ILOAD = 70 mA 4.8 5.0 5.2 V
FEEDBACK
V(FB1), V(FB2) Feedback voltage TJ = 25°C 0.5 V
Temperature accuracy TJ = –55°C to 125°C –1.25% +1.25%
Load regulation TA = +25°C, over IOUT range 0.2%
Line regulation TA = +25°C, IOUT = 0 A, over VIN range 0.1%
OUTPUT CURRENT
IOUT Output current Per channel 0 6(2) A
Overcurrent threshold source current DC current 6.6 A
Overcurrent threshold sink current DC current -2.8 A
ISH(acc) Output current sharing accuracy IOUT ≥ 3 A per channel 15%
IOUT < 3 A per channel 1 A
OCP hiccup wait time Wait time to attempt re-start 7 ms
OCP hiccup entry time Cycles before hiccup 16 cycles
SOFT START
tSS Default soft-start time Time from switching to PGOOD high without CSS 1 ms
ISS Soft-start charge current TSS ≤ 50 ms, CSS < 0.3 µF 2 µA
Rss Soft-start discharge resistance 600 Ω
ENABLE (EN)
VEN Enable threshold voltage EN rising 1.2 1.3 V
EN falling 1 1.1 V
Hysteresis on Enable 100 mV
Enable pullup current EN floating 1.4 µA
Enable to start switching time VIN ≥ 4.5 V, toggle EN 0.3 ms
SWITCH NODE (SW)
SW1, SW2 Discharge FET 32 Ω
SW1, SW2 minimum on time 40 50 ns
SW1, SW2 minimum off time 150 200 ns
SWITCHING FREQUENCY
Fsw1 MODE2 resistor = 10.7 kΩ 450 500 550 kHz
Fsw2 MODE2 resistor = 17.4 kΩ 900 1000 1100 kHz
Fsw3 MODE2 resistor = 28.7 kΩ 1350 1500 1650 kHz
Fsw4 MODE2 resistor = 53.6 kΩ 1800 2000 2200 kHz
SYNCHRONIZATION (SYNC)
VIH(SYNC) High-level input 2 V
VIL(sync) Low-level input 0.6 V
Input duty cycle 20% 80%
Sync frequency versus internal oscillator setting -20% +20%
CLOCK OUTPUT (CLKO)
VOH(CLKO) High-level output IO = 20 µA 2.2 V
VOL(CLKO) Low-level output IO = 20 µA 0.4 V
Pulse width output 80 ns
POWER GOOD WARNING (PGOOD1, PGOOD2)
PGOOD PGOOD thresholds VFB1, VFB2 falling (warning) 87% 90% 93%
VFB1, VFB2 rising (good) 90% 93% 96%
VFB1, VFB2 falling (good) 104% 107% 110%
VFB1, VFB2 rising (warning) 107% 110% 113%
PGOOD leakage current VPGOOD = 5.5 V 1 µA
PGOOD output low voltage BP5 = 5 V, IPGOOD = 6mA 0.5 V
Minimum VIN for asserted output VPGOOD ≤ 0.5 V, IPGOOD = 1 mA 1.5 V
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE FAULT PROTECTION
OV fault threshold VFB1, VFB2 rising (fault) 120%
UV fault threshold VFB1, VFB2 falling (fault) 80%
(1) See the Minimum and Maximum Input Voltage section for the recommended minimum input voltage at higher output voltages.
(2) See Safe Operating Area plots in the Typical Characteristics sections of the data sheet.