The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application circuit is shown in Figure 9-22. From 0 V to 0.6 V, the internal reference voltage to the internal error amplifier follows the SS/TR pin voltage. When the SS/TR pin voltage is above 0.6 V, the voltage tracking is disabled and the FB pin voltage is regulated at 0.6 V. The device achieves ratiometric, as shown in Figure 9-23 or coincidental (simultaneous) output tracking, as shown in Figure 9-23.

The R₂ value must be set properly to achieve accurate voltage tracking by taking the 10-μA charging current into account. 1 kΩ or smaller is a sufficient value for R₂. For decreasing SS/TR pin voltage, the device does not sink current from the output when the device is in PSM. The resulting decrease of the output voltage can be slower than the SS/TR pin voltage if the load is light.

In case both devices need to run in forced PWM mode after start-up, TI recommends to tie the MODE/SYNC pin of the secondary device to the output voltage or the power good signal of the primary device. The TPSM82816 has a duty cycle limitation defined by the minimum on time. For tracking down to low output voltages, the secondary device cannot follow after the minimum duty cycle is reached. Enabling FPWM mode while tracking is in progress allows the user to ramp down the output voltage close to 0 V.

When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin.

Figure 9-22 Schematic for Output Voltage Tracking