SLVSDF3F MARCH   2017  – JANUARY 2019 TPSM846C23

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Programmable Characteristics
    8. 6.8 Typical Characteristics (VIN = 12 V)
    9. 6.9 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PMBus
        1. 7.3.1.1 PMBus General Description
        2. 7.3.1.2 PMBus Address
        3. 7.3.1.3 PMBus Connections
        4. 7.3.1.4 Supported PMBus Commands
      2. 7.3.2  Minimum Capacitance Requirements
      3. 7.3.3  Setting the Compensation Network
      4. 7.3.4  Transient Response
      5. 7.3.5  Setting the Output Voltage via PMBus
      6. 7.3.6  Setting the Output Voltage Without PMBus
      7. 7.3.7  Differential Remote Sense
      8. 7.3.8  Voltage Reference
      9. 7.3.9  Switching Frequency and Synchronization
        1. 7.3.9.1 Setting the Switching Frequency
        2. 7.3.9.2 Synchronization
          1. 7.3.9.2.1 Stand-Alone Device
          2. 7.3.9.2.2 Paralleled Devices
      10. 7.3.10 Input Undervoltage Lockout (UVLO)
      11. 7.3.11 Turnon and Turnoff Delay and Sequencing
      12. 7.3.12 Soft-Start Time and TON_RISE Command
      13. 7.3.13 Soft-Stop Time and TOFF_FALL Command
      14. 7.3.14 Prebiased Output Start-Up
      15. 7.3.15 Power Good (PGOOD) Indicator
      16. 7.3.16 Linear Regulators BP3 and BP6
      17. 7.3.17 VREF_TRIM
      18. 7.3.18 MARGIN
      19. 7.3.19 Parallel Application
      20. 7.3.20 Parallel Operation
      21. 7.3.21 Telemetry
        1. 7.3.21.1 Output Current Telemetry
        2. 7.3.21.2 Output Voltage Telemetry
        3. 7.3.21.3 Junction Temperature Telemetry
      22. 7.3.22 Overtemperature Protection
      23. 7.3.23 Overcurrent Protection
      24. 7.3.24 Output Overvoltage and Undervoltage Protection
      25. 7.3.25 Fault Protection Responses
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With CNTL Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With CNTL and OPERATION Control
    5. 7.5 Register Maps
      1. 7.5.1  OPERATION (01h)
        1. 7.5.1.1 On Bit
        2. 7.5.1.2 Off Bit
        3. 7.5.1.3 Margin Bit
      2. 7.5.2  ON_OFF_CONFIG (02h)
        1. 7.5.2.1 pu Bit
        2. 7.5.2.2 cmd Bit
        3. 7.5.2.3 cpr Bit
        4. 7.5.2.4 pol Bit
        5. 7.5.2.5 cpa Bit
      3. 7.5.3  CLEAR_FAULTS (03h)
      4. 7.5.4  WRITE_PROTECT (10h)
        1. 7.5.4.1 bit5
        2. 7.5.4.2 bit6
        3. 7.5.4.3 bit7
      5. 7.5.5  STORE_DEFAULT_ALL (11h)
      6. 7.5.6  RESTORE_DEFAULT_ALL (12h)
      7. 7.5.7  STORE_USER_ALL (15h)
      8. 7.5.8  RESTORE_USER_ALL (16h)
      9. 7.5.9  CAPABILITY (19h)
      10. 7.5.10 SMBALERT_MASK (1Bh)
      11. 7.5.11 VOUT_MODE (20h)
        1. 7.5.11.1 Mode Bit
        2. 7.5.11.2 Exponent Bit
      12. 7.5.12 VOUT_COMMAND (21h)
        1. 7.5.12.1 Exponent
        2. 7.5.12.2 Mantissa
      13. 7.5.13 VOUT_MAX (24h)
        1. 7.5.13.1 Exponent
        2. 7.5.13.2 Mantissa
      14. 7.5.14 VOUT_TRANSITION_RATE (27h)
        1. 7.5.14.1 Exponent
        2. 7.5.14.2 Mantissa
      15. 7.5.15 VOUT_SCALE_LOOP (29h)
        1. 7.5.15.1 Exponent
        2. 7.5.15.2 Mantissa
      16. 7.5.16 VOUT_MIN (2Bh)
        1. 7.5.16.1 Exponent
        2. 7.5.16.2 Mantissa
      17. 7.5.17 VIN_ON (35h)
        1. 7.5.17.1 Exponent
        2. 7.5.17.2 Mantissa
      18. 7.5.18 VIN_OFF (36h)
        1. 7.5.18.1 Exponent
        2. 7.5.18.2 Mantissa
      19. 7.5.19 IOUT_CAL_OFFSET (39h)
        1. 7.5.19.1 Exponent
        2. 7.5.19.2 Mantissa
      20. 7.5.20 VOUT_OV_FAULT_RESPONSE (41h)
        1. 7.5.20.1 RSP[1] Bit
        2. 7.5.20.2 RS[2:0] Bits
        3. 7.5.20.3 TD[2:0] Bits
      21. 7.5.21 VOUT_UV_FAULT_RESPONSE (45h)
        1. 7.5.21.1 RSP[1] Bit
        2. 7.5.21.2 RS[2:0] Bits
        3. 7.5.21.3 TD[2:0] Bits
      22. 7.5.22 IOUT_OC_FAULT_LIMIT (46h)
        1. 7.5.22.1 Exponent
        2. 7.5.22.2 Mantissa
      23. 7.5.23 IOUT_OC_FAULT_RESPONSE (47h)
        1. 7.5.23.1 RSP[1:0] Bits
        2. 7.5.23.2 RS[2:0] Bits
        3. 7.5.23.3 TD[2:0] Bits
      24. 7.5.24 IOUT_OC_WARN_LIMIT (4Ah)
        1. 7.5.24.1 Exponent
        2. 7.5.24.2 Mantissa
      25. 7.5.25 OT_FAULT_LIMIT (4Fh)
        1. 7.5.25.1 Exponent
        2. 7.5.25.2 Mantissa
      26. 7.5.26 OT_FAULT_RESPONSE (50h)
        1. 7.5.26.1 RSP[1] Bit
        2. 7.5.26.2 RS[2:0] Bits
        3. 7.5.26.3 TD[2:0] Bits
      27. 7.5.27 OT_WARN_LIMIT (51h)
        1. 7.5.27.1 Exponent
        2. 7.5.27.2 Mantissa
      28. 7.5.28 TON_DELAY (60h)
        1. 7.5.28.1 Exponent
        2. 7.5.28.2 Mantissa
      29. 7.5.29 TON_RISE (61h)
        1. 7.5.29.1 Exponent
        2. 7.5.29.2 Mantissa
      30. 7.5.30 TON_MAX_FAULT_LIMIT (62h)
        1. 7.5.30.1 Exponent
        2. 7.5.30.2 Mantissa
      31. 7.5.31 TON_MAX_FAULT_RESPONSE (63h)
        1. 7.5.31.1 RSP[1] Bit
        2. 7.5.31.2 RS[2:0] Bits
        3. 7.5.31.3 TD[2:0] Bits
      32. 7.5.32 TOFF_DELAY (64h)
        1. 7.5.32.1 Exponent
        2. 7.5.32.2 Mantissa
      33. 7.5.33 TOFF_FALL (65h)
        1. 7.5.33.1 Exponent
        2. 7.5.33.2 Mantissa
      34. 7.5.34 STATUS_BYTE (78h)
      35. 7.5.35 STATUS_WORD (79h)
      36. 7.5.36 STATUS_VOUT (7Ah)
      37. 7.5.37 STATUS_IOUT (7Bh)
      38. 7.5.38 STATUS_INPUT (7Ch)
      39. 7.5.39 STATUS_TEMPERATURE (7Dh)
      40. 7.5.40 STATUS_CML (7Eh)
      41. 7.5.41 STATUS_MFR_SPECIFIC (80h)
      42. 7.5.42 READ_VOUT (8Bh)
        1. 7.5.42.1 Exponent
        2. 7.5.42.2 Mantissa
      43. 7.5.43 READ_IOUT (8Ch)
        1. 7.5.43.1 Exponent
        2. 7.5.43.2 Mantissa
      44. 7.5.44 READ_TEMPERATURE_1 (8Dh)
        1. 7.5.44.1 Exponent
        2. 7.5.44.2 Mantissa
      45. 7.5.45 PMBUS_REVISION (98h)
      46. 7.5.46 IC_DEVICE_ID (ADh)
      47. 7.5.47 IC_DEVICE_REV (AEh)
      48. 7.5.48 MFR_SPECIFIC_00 (D0h)
      49. 7.5.49 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
      50. 7.5.50 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
      51. 7.5.51 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
      52. 7.5.52 PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h)
      53. 7.5.53 OPTIONS (MFR_SPECIFIC_21) (E5h)
        1. 7.5.53.1  DIS_NEGILIM Bit
        2. 7.5.53.2  EN_RESET_B Bit
        3. 7.5.53.3  EN_ADC_CNTL Bit
        4. 7.5.53.4  VSM Bit
        5. 7.5.53.5  DLO Bit
        6. 7.5.53.6  AVG_PROG[1:0] Bits
        7. 7.5.53.7  EN_AUTO_ARA Bit
        8. 7.5.53.8  READ_VOUT_RANGE[1:0] Bits
        9. 7.5.53.9  RST_VOUT_oSD Bit
        10. 7.5.53.10 RSMLO_VAL Bit
        11. 7.5.53.11 RSMHI_VAL Bit
      54. 7.5.54 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)
        1. 7.5.54.1 OV_RESP_SEL Bit
        2. 7.5.54.2 HSOC_USER_TRIM[1:0] Bits
        3. 7.5.54.3 EN_AVS_USER Bit
        4. 7.5.54.4 FORCE_SYNC_OUT Bit
        5. 7.5.54.5 FORCE_SYNC_IN Bit
        6. 7.5.54.6 SYNC_FAULT_DIS Bit
  8. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
        2. 8.1.2.2 Setting the Output Voltage
        3. 8.1.2.3 Input and Output Capacitance
        4. 8.1.2.4 Selecting the Compensation Components
        5. 8.1.2.5 Setting the Switching Frequency
        6. 8.1.2.6 Power Good (PGOOD)
        7. 8.1.2.7 ON/OFF Control (CNTL)
      3. 8.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Specifications
    4. 10.4 EMI
    5. 10.5 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.27 OT_WARN_LIMIT (51h)

The OT_WARN_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an overtemperature warning condition, when the sensed temperature from the internal sensor exceeds this limit. Upon triggering the overtemperature warning, the device takes the following actions:

Once the overtemperature warning is tripped, the warning flag is latched until the internal sensed temperature decreases 20°C from the OT_WARN_LIMIT.

The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. In such case, the register content will remain unchanged. This behavior can be overridden by the user setting Data Limit Override (DLO) in MFR_SPECIFIC_21[4].

The default OT_WARN_LIMIT is mathematically derived from the EEPROM backed OTF limit by subtracting 25 from (4Fh) OT_FAULT_LIMIT to reach the default OT_WARN_LIMIT. If the calculated OTW is less than 100°C, then the default value is set to 100°C. OTW=max(OTF-25, 100)

The OT_WARN_LIMIT takes a two byte data word formatted as shown below:

COMMAND OT_WARN_LIMIT
Format Unsigned binary
Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w
Function Exponent Mantissa
Default Value 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0