SLVSDF3F MARCH 2017 – JANUARY 2019 TPSM846C23
The TPSM846C23 device prevents current from being discharged from the output during start-up when a prebiased output condition exists. If the output is prebiased, no PH pulses occur until the internal soft-start voltage rises above the error-amplifier input voltage (FB pin). As soon as the soft-start voltage exceeds the error-amplifier input, and PH pulses start. The device limits synchronous rectification after each PH pulse with a narrow on-time. The on-time of the low-side MOSFET slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of current from a prebiased output and ensures the output-voltage start-up and ramp-to-regulation sequences are smooth and monotonic.
If the prebias voltage is close to, or exceeds, the VOUT setpoint voltage, the mandatory 128 switching cycles, as previously described, may induce a non-monotonic dip in the output voltage. The output voltage quickly recovers to the setpoint value once the 128 cycle interval is completed.
The output overvoltage warn is tripped when the FB pin is prebiased to higher than 5% above the regulation level. These devices respond to a prebiased output overvoltage condition immediately upon VIN powered up and when the BP6 regulator voltage is above the BP6 UVLO of 3.73 V (typical).