SLUSEN7A August   2022  – September 2023 TPSM8D6B24

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Average Current-Mode Control
        1. 7.3.1.1 On-Time Modulator
        2. 7.3.1.2 Current Error Integrator
        3. 7.3.1.3 Voltage Error Integrator
      2. 7.3.2  Linear Regulators
      3. 7.3.3  AVIN and PVIN Pins
      4. 7.3.4  Input Undervoltage Lockout (UVLO)
        1. 7.3.4.1 Fixed AVIN UVLO
        2. 7.3.4.2 Fixed VDD5 UVLO
        3. 7.3.4.3 Programmable PVIN UVLO
        4. 7.3.4.4 EN/UVLO Pin
      5. 7.3.5  Start-Up and Shutdown
      6. 7.3.6  Differential Sense Amplifier and Feedback Divider
      7. 7.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 7.3.7.1 Reset Output Voltage
        2. 7.3.7.2 Soft Start
      8. 7.3.8  Prebiased Output Start-Up
      9. 7.3.9  Soft Stop and (65h) TOFF_FALL Command
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Set Switching Frequency
      12. 7.3.12 Frequency Synchronization
      13. 7.3.13 Loop Follower Detection
      14. 7.3.14 Current Sensing and Sharing
      15. 7.3.15 Telemetry
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage and Undervoltage Protection
      18. 7.3.18 Overtemperature Management
      19. 7.3.19 Fault Management
      20. 7.3.20 Back-Channel Communication
      21. 7.3.21 Switching Node (SW)
      22. 7.3.22 PMBus General Description
      23. 7.3.23 PMBus Address
      24. 7.3.24 PMBus Connections
    4. 7.4 Device Functional Modes
      1. 7.4.1 Programming Mode
      2. 7.4.2 Standalone, Loop Controller, and Loop Follower Mode Pin Connections
      3. 7.4.3 Continuous Conduction Mode
      4. 7.4.4 Operation With CNTL Signal (EN/UVLO)
      5. 7.4.5 Operation with (01h) OPERATION Control
      6. 7.4.6 Operation with CNTL and (01h) OPERATION Control
    5. 7.5 Programming
      1. 7.5.1 Supported PMBus Commands
      2. 7.5.2 Pin Strapping
        1. 7.5.2.1 Programming MSEL1
        2. 7.5.2.2 Programming MSEL2
        3. 7.5.2.3 Programming VSEL
        4. 7.5.2.4 Programming ADRSEL
        5. 7.5.2.5 Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5)
        6. 7.5.2.6 Pin-Strapping Resistor Configuration
    6. 7.6 Register Maps
      1. 7.6.1  Conventions for Documenting Block Commands
      2. 7.6.2  (01h) OPERATION
      3. 7.6.3  (02h) ON_OFF_CONFIG
      4. 7.6.4  (03h) CLEAR_FAULTS
      5. 7.6.5  (04h) PHASE
      6. 7.6.6  (10h) WRITE_PROTECT
      7. 7.6.7  (15h) STORE_USER_ALL
      8. 7.6.8  (16h) RESTORE_USER_ALL
      9. 7.6.9  (19h) CAPABILITY
      10. 7.6.10 (1Bh) SMBALERT_MASK
      11. 7.6.11 (1Bh) SMBALERT_MASK_VOUT
      12. 7.6.12 (1Bh) SMBALERT_MASK_IOUT
      13. 7.6.13 (1Bh) SMBALERT_MASK_INPUT
      14. 7.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
      15. 7.6.15 (1Bh) SMBALERT_MASK_CML
      16. 7.6.16 (1Bh) SMBALERT_MASK_OTHER
      17. 7.6.17 (1Bh) SMBALERT_MASK_MFR
      18. 7.6.18 (20h) VOUT_MODE
      19. 7.6.19 (21h) VOUT_COMMAND
      20. 7.6.20 (22h) VOUT_TRIM
      21. 7.6.21 (24h) VOUT_MAX
      22. 7.6.22 (25h) VOUT_MARGIN_HIGH
      23. 7.6.23 (26h) VOUT_MARGIN_LOW
      24. 7.6.24 (27h) VOUT_TRANSITION_RATE
      25. 7.6.25 (29h) VOUT_SCALE_LOOP
      26. 7.6.26 (2Bh) VOUT_MIN
      27. 7.6.27 (33h) FREQUENCY_SWITCH
      28. 7.6.28 (35h) VIN_ON
      29. 7.6.29 (36h) VIN_OFF
      30. 7.6.30 (37h) INTERLEAVE
      31. 7.6.31 (38h) IOUT_CAL_GAIN
      32. 7.6.32 (39h) IOUT_CAL_OFFSET
      33. 7.6.33 (40h) VOUT_OV_FAULT_LIMIT
      34. 7.6.34 (41h) VOUT_OV_FAULT_RESPONSE
      35. 7.6.35 (42h) VOUT_OV_WARN_LIMIT
      36. 7.6.36 (43h) VOUT_UV_WARN_LIMIT
      37. 7.6.37 (44h) VOUT_UV_FAULT_LIMIT
      38. 7.6.38 (45h) VOUT_UV_FAULT_RESPONSE
      39. 7.6.39 (46h) IOUT_OC_FAULT_LIMIT
      40. 7.6.40 (47h) IOUT_OC_FAULT_RESPONSE
      41. 7.6.41 (4Ah) IOUT_OC_WARN_LIMIT
      42. 7.6.42 (4Fh) OT_FAULT_LIMIT
      43. 7.6.43 (50h) OT_FAULT_RESPONSE
      44. 7.6.44 (51h) OT_WARN_LIMIT
      45. 7.6.45 (55h) VIN_OV_FAULT_LIMIT
      46. 7.6.46 (56h) VIN_OV_FAULT_RESPONSE
      47. 7.6.47 (58h) VIN_UV_WARN_LIMIT
      48. 7.6.48 (60h) TON_DELAY
      49. 7.6.49 (61h) TON_RISE
      50. 7.6.50 (62h) TON_MAX_FAULT_LIMIT
      51. 7.6.51 (63h) TON_MAX_FAULT_RESPONSE
      52. 7.6.52 (64h) TOFF_DELAY
      53. 7.6.53 (65h) TOFF_FALL
      54. 7.6.54 (78h) STATUS_BYTE
      55. 7.6.55 (79h) STATUS_WORD
      56. 7.6.56 (7Ah) STATUS_VOUT
      57. 7.6.57 (7Bh) STATUS_IOUT
      58. 7.6.58 (7Ch) STATUS_INPUT
      59. 7.6.59 (7Dh) STATUS_TEMPERATURE
      60. 7.6.60 (7Eh) STATUS_CML
      61. 7.6.61 (7Fh) STATUS_OTHER
      62. 7.6.62 (80h) STATUS_MFR_SPECIFIC
      63. 7.6.63 (88h) READ_VIN
      64. 7.6.64 (8Bh) READ_VOUT
      65. 7.6.65 (8Ch) READ_IOUT
      66. 7.6.66 (8Dh) READ_TEMPERATURE_1
      67. 7.6.67 (98h) PMBUS_REVISION
      68. 7.6.68 (99h) MFR_ID
      69. 7.6.69 (9Ah) MFR_MODEL
      70. 7.6.70 (9Bh) MFR_REVISION
      71. 7.6.71 (9Eh) MFR_SERIAL
      72. 7.6.72 (ADh) IC_DEVICE_ID
      73. 7.6.73 (AEh) IC_DEVICE_REV
      74. 7.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
      75. 7.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
      76. 7.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
      77. 7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
      78. 7.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
      79. 7.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
      80. 7.6.80 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)
      81. 7.6.81 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
      82. 7.6.82 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
      83. 7.6.83 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
      84. 7.6.84 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
      85. 7.6.85 (EFh) MFR_SPECIFIC_31 (DEVICE_ADDRESS)
      86. 7.6.86 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
      87. 7.6.87 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
      88. 7.6.88 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
      89. 7.6.89 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Capacitor Selection
          1. 8.2.2.3.1 Output Voltage Deviation During Load Transient
          2. 8.2.2.3.2 Output Voltage Ripple
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  AVIN, BP1V5, and VDD5 Bypass Capacitor
        6. 8.2.2.6  Bootstrap Capacitor Selection
        7. 8.2.2.7  Output Voltage Setting (VSEL Pin)
        8. 8.2.2.8  R-C Snubber
        9. 8.2.2.9  Output Voltage Setting (VSEL Pin)
        10. 8.2.2.10 Compensation Selection (MSEL1 Pin)
        11. 8.2.2.11 Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        12. 8.2.2.12 Enable and UVLO
        13. 8.2.2.13 ADRSEL
        14. 8.2.2.14 Pin-Strapping Resistor Selection
        15. 8.2.2.15 BCX_CLK and BCX_DAT
      3. 8.2.3 Application Curves
    3. 8.3 Two-Phase Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1  Switching Frequency
        2. 8.3.2.2  Output Capacitor Selection
        3. 8.3.2.3  Input Capacitor Selection
        4. 8.3.2.4  AVIN, BP1V5, VDD5 Bypass Capacitor
        5. 8.3.2.5  Bootstrap Capacitor Selection
        6. 8.3.2.6  R-C Snubber
          1. 8.3.2.6.1 Output Voltage Setting (VSEL Pin)
        7. 8.3.2.7  Compensation Selection (MSEL1 Pin)
        8. 8.3.2.8  GOSNS/Loop Follower Pin of Loop Follower Devices
        9. 8.3.2.9  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        10. 8.3.2.10 Enable, UVLO
        11. 8.3.2.11 VSHARE Pin
          1. 8.3.2.11.1 ADRSEL Pin
        12. 8.3.2.12 SYNC Pin
        13. 8.3.2.13 VOSNS Pin of Loop Follower Devices
        14. 8.3.2.14 Unused Pins of Loop Follower Devices
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Thermal Performance on the TI EVM
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Texas Instruments Fusion Digital Power Designer
        2. 9.1.2.2 Custom Design With WEBENCH® Tools
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • MOW|59
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.80 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)

CMD AddressE3h
Write Transaction:Write Word
Read Transaction:Read Word
FormatUnsigned Word
Phased:No
NVM Backup:EEPROM or Pin Detect
Updates:Conversion Disable: see below. Conversion Enable: Read-Only
Figure 7-86 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG) Register Map
15141312111098
RRRRRRRR
PGOOD_OFF_DELAY[3:0]PGOOD_ON_DELAY[3:0]
76543210
RRRRRWRWRWRW
pgmOVFpgmOVWpgmUVWpgmUVFpgmOCWpgmOCFpgmINOVWpgmINOVF
LEGEND: R/W = Read/Write; R = Read only
Table 7-97 Register Field Descriptions

Bit

Field

Access

Reset

Description

15:12

PGOOD_OFF_DELAY[3:0]

RW

NVMSets delay from the detection of an unmasked fault or warning event to the assertion of PGOOD low.
0d: Delay PGOOD high-low 1 PWM CLK
1d - 15d: Delay PGOOD high-low 2N + 1 PWM CLKs

11:8

PGOOD_ON_DELAY[3:0]

RW

NVMSets delay from the detection of no unmasked fault or warning events to the release of PGOOD low.
0d: Delay PGOOD low-hight to 1 PWM CLK
1d - 15d: Delay PGOOD low-high 2N + 1 PWM CLKs

7

pgmOVF

RW

NVM

0b: Output overvoltage fault can assert PGOOD low.
1b: Output overvoltage fault cannot assert PGOOD low.

6

pgmOVW

RW

NVM

0b: Output overvoltage warning can assert PGOOD low.
1b: Output overvoltage warning cannot assert PGOOD low.

5

pgmUVF

RW

NVM

0b: Output undervoltage fault can assert PGOOD low.
1b: Output undervoltage fault cannot assert PGOOD low.

4

pgmUVW

RW

NVM

0b: Output undervoltage warning can assert PGOOD low.
1b: Output undervoltage warning cannot assert PGOOD low.

3

pgmOCW

RW

NVM

0b: Output overcurrent warning can assert PGOOD low.
1b: Output overcurrent warning cannot assert PGOOD low.

2

pgmOCF

RW

NVM

0b: Output overcurrent fault can assert PGOOD low.
1b: Output overcurrent fault cannot assert PGOOD low.

1

pgmINOVW

RW

NVM

0b: Input overvoltage warning can assert PGOOD low.
1b: Input overvoltage warning cannot assert PGOOD low.

0

pgmINOVF

RW

NVM

0b: Input overvoltage fault can assert PGOOD low.
1b: Input overvoltage fault cannot assert PGOOD low.

Power good indicates the status of the converter. (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG) provides control of the delays asserting and releasing power good. Power good is always low while conversion is disabled, during (60h) TON_DELAY, (61h) TON_RISE, (65h) TOFF_FALL, and during a fault shutdown or hiccup delay. PGOOD_OFF_DELAY is bypassed during (65h) TOFF_FALL and during a fault shutdown or hiccup. Power good is still asserted on an unmasked fault event unless the RESPONSE command of that fault is configured to continue operating without interruption.

PGOOD_OFF_DELAY and PGOOD_ON_DELAY are sensed and timed independently from each other. If PGOOD_ON_DELAY is less than PGOOD_OFF_DELAY and an unmasked fault or warning event lasts less than PGOOD_OFF_DELAY – PGOOD_ON_DELAY, power good is not asserted low during the fault or warning events.