SLOS757G December   2011  – March 2020 TRF7962A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1  Command Codes
      2. 6.13.2  Reset FIFO (0x0F)
      3. 6.13.3  Transmission With CRC (0x11)
      4. 6.13.4  Transmission Without CRC (0x10)
      5. 6.13.5  Transmit Next Time Slot (0x14)
      6. 6.13.6  Block Receiver (0x16)
      7. 6.13.7  Enable Receiver (0x17)
      8. 6.13.8  Test Internal RF (RSSI at RX Input With TX On) (0x18)
      9. 6.13.9  Test External RF (RSSI at RX Input With TX Off) (0x19)
      10. 6.13.10 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1 TX Pulse Length Control Register (0x06)
          2. 6.14.1.2.2 RX No Response Wait Time Register (0x07)
          3. 6.14.1.2.3 RX Wait Time Register (0x08)
          4. 6.14.1.2.4 Modulator and SYS_CLK Control Register (0x09)
          5. 6.14.1.2.5 RX Special Setting Register (0x0A)
          6. 6.14.1.2.6 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7962A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.14.1.2.4 Modulator and SYS_CLK Control Register (0x09)

Table 6-22 describes the bit fields of the Modulator and SYS_CLK Control register. This register controls the modulation input and depth, ASK/OOK pin control, and clock output to an external system (an MCU).

Default Value: 0x11, set at POR = H or EN = L at each write to the ISO Control register for all bits except Clo1 and Clo0

The frequency of SYS_CLK (pin 27) is programmable by bits B4 and B5 of this register. The frequency of the TRF7962A system clock oscillator is divided by 1, 2, or 4 resulting in available SYS_CLK frequencies of 13.56 MHz, 6.78 MHz, or 3.39 MHz, respectively.

The ASK modulation depth is controlled by bits B0, B1, and B2. The range of ASK modulation is 7% to 30% or 100% (OOK). The selection between ASK and OOK (100%) modulation can also be done using direct input OOK (pin 12). The direct control of OOK or ASK using the OOK pin is only possible if the function is enabled by setting B6 = 1 (en_ook_p) in this register (0x09) and the ISO Control register (0x01, B6 = 1). When configured this way, the MOD pin (pin 14) is used as input for the modulation signal.

Table 6-22 Modulator and SYS_CLK Control Register (0x09)

BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 Unused
B6 en_ook_p

1 = Enables external selection of ASK or OOK modulation

0 = Default operation as defined in bits B0 to B2 of this register

 Enable ASK/OOK pin (pin 12) for change between any preselected ASK modulation as defined by B0 to B2 and OOK modulation.

If B6 is set to 1, pin 12 is configured as:
1 = OOK modulation
0 = Modulation as defined in B0 to B2 (0x09)
B5 Clo1 SYS_CLK output frequency. B5 is the MSB. Clo1 Clo0 SYS_CLK Output
0 0 Disabled
0 1 3.39 MHz
B4 Clo0 1 0 6.78 MHz
1 1 13.56 MHz
B3 en_ana

1 = Sets pin 12 (ASK/OOK) as an analog output

0 = Default

 For test and measurement purpose. ASK/OOK pin 12 can be used to monitor the analog subcarrier signal before the digitizing with DC level equal to AGND.
B2 Pm2 Modulation depth. B2 is the MSB. Pm2 Pm1 Pm0 Modulation Type and Percentage
0 0 0 ASK 10%
0 0 1 OOK (100%)
B1 Pm1 0 1 0 ASK 7%
0 1 1 ASK 8.5%
1 0 0 ASK 13%
B0 Pm0 1 0 1 ASK 16%
1 1 0 ASK 22%
1 1 1 ASK 30%