SLOS758G December   2011  – March 2020 TRF7963A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
      2. 6.13.2 Reset FIFO (0x0F)
      3. 6.13.3 Transmission With CRC (0x11)
      4. 6.13.4 Transmission Without CRC (0x10)
      5. 6.13.5 Block Receiver (0x16)
      6. 6.13.6 Enable Receiver (0x17)
      7. 6.13.7 Test Internal RF (RSSI at RX Input With TX On) (0x18)
      8. 6.13.8 Test External RF (RSSI at RX Input With TX Off) (0x19)
      9. 6.13.9 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1 ISO14443B TX Options Register (0x02)
          2. 6.14.1.2.2 ISO14443A High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.1.2.3 TX Pulse Length Control Register (0x06)
          4. 6.14.1.2.4 RX No Response Wait Time Register (0x07)
          5. 6.14.1.2.5 RX Wait Time Register (0x08)
          6. 6.14.1.2.6 Modulator and SYS_CLK Control Register (0x09)
          7. 6.14.1.2.7 RX Special Setting Register (0x0A)
          8. 6.14.1.2.8 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7963A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.14.1 Register Overview

Table 6-15 lists the registers available in the TRF7963A. These registers are described in the following sections.

Table 6-15 Register Overview

ADDRESS
(hex)		 REGISTER READ/WRITE SECTION
Main Control Registers
0x00 Chip Status Control R/W Section 6.14.1.1.1
0x01 ISO Control R/W Section 6.14.1.1.2
Protocol Subsetting Registers
0x02 ISO14443B TX Options R/W Section 6.14.1.2.1
0x03 ISO14443A High-Bit-Rate Options R/W Section 6.14.1.2.2
0x06 TX Pulse-Length Control R/W Section 6.14.1.2.3
0x07 RX No Response Wait R/W Section 6.14.1.2.4
0x08 RX Wait Time R/W Section 6.14.1.2.5
0x09 Modulator and SYS_CLK Control R/W Section 6.14.1.2.6
0x0A RX Special Setting R/W Section 6.14.1.2.7
0x0B Regulator and I/O Control R/W Section 6.14.1.2.8
Status Registers
0x0C IRQ Status R Section 6.14.1.3.1
0x0D Collision Position and Interrupt Mask Register R/W Section 6.14.1.3.2
0x0E Collision Position R Section 6.14.1.3.2
0x0F RSSI Levels and Oscillator Status R Section 6.14.1.3.3
FIFO Registers
0x1A Test R/W Section 6.14.1.4.1
0x1B Test R/W Section 6.14.1.4.2
0x1C FIFO Status R Section 6.14.1.5.1
0x1D TX Length Byte1 R/W Section 6.14.1.5.2
0x1E TX Length Byte2 R/W Section 6.14.1.5.2
0x1F FIFO I/O Register R/W