SLOS758G December   2011  – March 2020 TRF7963A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
      2. 6.13.2 Reset FIFO (0x0F)
      3. 6.13.3 Transmission With CRC (0x11)
      4. 6.13.4 Transmission Without CRC (0x10)
      5. 6.13.5 Block Receiver (0x16)
      6. 6.13.6 Enable Receiver (0x17)
      7. 6.13.7 Test Internal RF (RSSI at RX Input With TX On) (0x18)
      8. 6.13.8 Test External RF (RSSI at RX Input With TX Off) (0x19)
      9. 6.13.9 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1 ISO14443B TX Options Register (0x02)
          2. 6.14.1.2.2 ISO14443A High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.1.2.3 TX Pulse Length Control Register (0x06)
          4. 6.14.1.2.4 RX No Response Wait Time Register (0x07)
          5. 6.14.1.2.5 RX Wait Time Register (0x08)
          6. 6.14.1.2.6 Modulator and SYS_CLK Control Register (0x09)
          7. 6.14.1.2.7 RX Special Setting Register (0x0A)
          8. 6.14.1.2.8 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7963A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)

Table 6-38 describes the bit fields of the TX Length Byte1 register. This register contains the high two nibbles of complete intended bytes to be transferred through FIFO.

Default Value: 0x00, set at POR and EN = 0. The register is also automatically reset at TX EOF.

Table 6-38 TX Length Byte1 Register (0x1D)

BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 Txl11 Number of complete byte bn[11] High nibble of complete intended bytes to be transmitted
B6 Txl10 Number of complete byte bn[10]
B5 Txl9 Number of complete byte bn[9]
B4 Txl8 Number of complete byte bn[8]
B3 Txl7 Number of complete byte bn[7] Middle nibble of complete intended bytes to be transmitted
B2 Txl6 Number of complete byte bn[6]
B1 Txl5 Number of complete byte bn[5]
B0 Txl4 Number of complete byte bn[4]

Table 6-39 describes the bit fields of the TX Length Byte2 register. This register contains the low nibble of the complete bytes to be transferred through FIFO, and information about a broken byte and number of bits to be transferred from it.

Default Value: 0x00, set at POR and EN = 0. The register is also automatically reset at TX EOF.

Table 6-39 TX Length Byte2 Register (0x1E)

BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 Txl3 Number of complete byte bn[3] Low nibble of complete intended bytes to be transmitted
B6 Txl2 Number of complete byte bn[2]
B5 Txl1 Number of complete byte bn[1]
B4 Txl0 Number of complete byte bn[0]
B3 Bb2 Broken byte number of bits bb[2] Number of bits in the last broken byte to be transmitted.

This value is taken into account only when broken byte flag is set.
B2 Bb1 Broken byte number of bits bb[1]
B1 Bb0 Broken byte number of bits bb[0]
B0 Bbf Broken byte flag B0 = 1 indicates that last byte is not complete 8 bits wide.