SLLSFO5A November   2021  – September 2022 TRSF3243E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings - IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics: Driver
    8. 6.8  Switching Characteristics: Driver
    9. 6.9  Electrical Characteristics: Receiver
    10. 6.10 Switching Characteristics: Receiver
    11. 6.11 Electrical Characteristics: Auto-Powerdown
    12. 6.12 Switching Characteristics: Auto-Powerdown
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2.     Functional Block Diagram
    3. 7.2 Feature Description
    4. 7.3 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
    4. 8.4 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1.      Device and Documentation Support
        1. 11.1 Receiving Notification of Documentation Updates
        2. 11.2 Support Resources
        3. 11.3 Trademarks
        4. 11.4 Electrostatic Discharge Caution
        5. 11.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics: Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS(3) TYP(1) UNIT
tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 7-3 150 ns
tPHL Propagation delay time, high- to low-level output CL = 150 pF, See Figure 7-3 150 ns
ten Output enable time CL = 150 pF, RL = 3 kΩ, See Figure 7-4 200 ns
tdis Output disable time CL = 150 pF, RL = 3 kΩ, See Figure 7-4 200 ns
tsk(p) Pulse skew(2) See Figure 7-3 50 ns
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
(3) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.