SCDS307D September   2010  – October 2022 TS3L501E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for 1000 Base-T Ethernet Switching
    6. 6.6 Electrical Characteristics for 10/100 Base-T Ethernet Switching
    7. 6.7 Switching Characteristics
    8. 6.8 Dynamic Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Enable and Disable Times
    2. 7.2 Skew
    3. 7.3 HP8753ES Setup
    4. 7.4 HP8753ES Setup
    5. 7.5 HP8753ES Setup
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-A866494F-6A9A-4779-9DF6-9D87CEDA0135-low.gif
The exposed center pad must be connected to GND.
Figure 5-1 RUA Package,42-Pin WQFN(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
A0 2 I/O Port A Common I/O signal path
A1 3 I/O Port A Common I/O signal path
A2 6 I/O Port A Common I/O signal path
A3 7 I/O Port A Common I/O signal path
A4 9 I/O Port A Common I/O signal path
A5 10 I/O Port A Common I/O signal path
A6 11 I/O Port A Common I/O signal path
A7 12 I/O Port A Common I/O signal path
B0 38 I/O Port B I/O signal path
B1 37 I/O Port B I/O signal path
B2 34 I/O Port B I/O signal path
B3 33 I/O Port B I/O signal path
B4 29 I/O Port B I/O signal path
B5 28 I/O Port B I/O signal path
B6 25 I/O Port B I/O signal path
B7 24 I/O Port B I/O signal path
C0 36 I/O Port C I/O signal path
C1 35 I/O Port C I/O signal path
C2 32 I/O Port C I/O signal path
C3 31 I/O Port C I/O signal path
C4 27 I/O Port C I/O signal path
C5 26 I/O Port C I/O signal path
C6 23 I/O Port C I/O signal path
C7 22 I/O Port C I/O signal path
GND Exposed Center Pad — Ground
LED_A0 15 I/O Port A LED I/O Common signal path, (may also be used as a general purpose signal path)
LED_A1 16 I/O Port A LED Common I/O signal path, (may also be used as a general purpose signal path)
LED_A2 42 I/O Port A LED Common I/O signal path, (may also be used as a general purpose signal path)
LED_B0 17 I/O Port B LED I/O signal path, (may also be used as a general purpose signal path)
LED_B1 18 I/O Port B LED I/O signal path, (may also be used as a general purpose signal path)
LED_B2 41 I/O Port B LED I/O signal path, (may also be used as a general purpose signal path)
LED_C0 19 I/O Port C LED I/O signal path, (may also be used as a general purpose signal path)
LED_C1 20 I/O Port C LED I/O signal path, (may also be used as a general purpose signal path)
LED_C2 40 I/O Port C LED I/O signal path, (may also be used as a general purpose signal path)
PD 5 I Power down input, active high
SEL 13 I Select input
VDD 1, 4, 8, 14, 21, 30, 39 — Power
(1) I = input, O = output