SLLSF73C February   2018  – September 2019 TS3USBCA4

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V)
    6. 6.6  Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
    7. 6.7  Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
    8. 6.8  Timing Requirements (3 V ≤ VCC ≤ 3.6 V)
    9. 6.9  Timing Requirements (2.4 V ≤ VCC ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Audio Path
      2. 8.3.2 High-Speed Paths
      3. 8.3.3 3-level Input
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 TS3USBCA4 Registers
        1. 8.6.1.1 Revision_ID Register (Offset = 9h) [reset = 0h]
          1. Table 8. Revision_ID Register Field Descriptions
        2. 8.6.1.2 General_1 Register (Offset = Ah) [reset = 0h]
          1. Table 9. General_1 Register Field Descriptions
        3. 8.6.1.3 General_2 Register (Offset = Bh) [reset = 0h]
          1. Table 10. General_2 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V)

All minimum/maximum specifications are at TA = -40/85°C, VCC = 2.4 V/5.5 V, unless otherwise noted. Typical specifications are at TA = 25°C, VCC = 3.3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
ICC Supply Current OEn = L, DEVICE_ENABLE = 1 45 75 μA
IOFF_I2C Device Shutdown Current OEn = L, DEVICE_ENABLE = 0 17 40 μA
IOFF_OEN Device Shutdown Current OEn = 3.6 V 0.05 5.5 μA
Device Shutdown Current OEn = 1.4 V 4 80 μA
SEL0, SEL1
VIH Input-high voltage 1.4 V
VIL Input-low voltage 0.4 V
IIH Input-high current VIN = VCC 3.5 µA
IIL Input-low current VIN = 0 V 1 µA
RPD Pull-down resistor 1.6 3.0 5.8 MΩ
FLIP
VIH Input-high voltage   1.4     V
VIL Input-low voltage     0.4 V
IIH Input-high current VIN = VCC     3.5 µA
IIL Input-low current VIN = 0 V     1 µA
RPD Pull-down resistor 1.6 3.0 5.8 MΩ
OEn
VIH Input-high voltage 1.5 V
VIL Input-low voltage 0.4 V
IIH Input-high current VIN=VCC 1 µA
IIL Input-low current VIN=0 V 8 µA
RPU Pull-up resistor 0.6 1.1 2.5 MΩ
I2C_EN
VIH Input-high voltage 0.9 VCC
VIMH Upper bound of mid-level input voltage. Higher input may be intepreted as logic HIGH. 0.58 VCC
VIML Lower bound of mid-level input voltage. Lower input may be intepreted as logic LOW. 0.42 VCC
VIL Input-low voltage 0.14 VCC
IIH Input-high current 3.5 µA
IIM Mid-level input current 1.6 µA
IIL Input-low current 1 µA
RPD Pull-down resistor 1.6 3.0 5.8 MΩ
I2C Control Pins SCL, SDA
VIH_I2C High-level input voltage I2C mode 1.3 VI2C V
VIL_I2C Low-level input voltage I2C mode 0 0.5 V
VOL_I2C Low-level output voltage I2C mode; IOL_I2C = 3 mA 0 0.4 V
IOL_I2C Low-level output current I2C mode; VOL_I2C = 0.4 V 4 mA
II_I2C Input current on SDA pin 0.1*VI2C < Input voltage < 3.6 V -5 5 µA
CI_I2C Input capacitance 0.5 10 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400 kHz) 150 pF
R(EXT_I2C_FM) External pull up resistors on both SDA and SCL for FM (400 kHz) C(I2C_FM_BUS) = 150 pF 620 1500 2200 Ω
SBU1, SBU2
CSBU_HS Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, high-speed path enabled 4 11 13 pF
CSBU_AUDIO Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V 8 10 14 pF
CSBU_OFF Single-ended capacitance at 500MHz looking into SBU pin VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V 11 14 17 pF
RPD Pull-down resistor 0.8 1.6 3.3 MΩ
LnA, LnB, LnC: HIGH-SPEED PATH
VI_HS Single-ended HS input voltage  -0.3 3.6 V
CHS_ON Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, high-speed path enabled 8.5 10.5 pF
CHS_AUDIO Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V   1.7 2 pF
CHS_OFF Single-ended capacitance at 500 MHz looking into HS pins VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V   1.7 2 pF
RON_HS ON resistance VIN = 0 V, IO = -40 mA   4.9 7.5 Ω
ΔRON_HS ON resistance match between pairs of the same channel VIN ≤ 0 V, IO = -40 mA   0.65 Ω
RON_FLAT_HS ON resistance flatness (RON_HS(MAX) - RON_HS(MIN)) 0 V ≤ VIN ≤ 3.6 V, IO = -40 mA   1.35 Ω
BWHS -3-dB bandwidth RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC = 3.3 V 450 510 670 MHz
RJHS Additive random jitter RL = 50 Ω, 10 kHz to 20 MHz offset, f = 100 MHz; TA = 25°C; VCC = 3.3 V 0.012 ps-RMS
MIC_GND1, MIC_GND2: AUDIO PATH
VI_MIC MIC input voltage -0.3 3.6 V
CAUDIO_ON Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, audio path enabled; TA = 25°C; VCC = 3.3 V   9.5 12 pF
CAUDIO_HS Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, high-speed path enabled; TA = 25°C; VCC = 3.3 V   11.5 16 pF
CAUDIO_OFF Single-ended capacitance at 500MHz looking into the MIC_GND pins VIN = 0 V, outputs open, OEn=H; TA = 25°C; VCC = 3.3 V   12.5 14.5 pF
RON_AUDIO ON resistance for AUDIO path VIN = 0 V, IO = -75 mA   50 80 mΩ
BWAUDIO -3-dB bandwidth RL = 50 Ω, VIN = 0 V; TA = 25°C; VCC = 3.3 V 580 630 720 MHz
PSR217 Power supply rejection RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 217 Hz   -105 -96 dB
PSR1K RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 1 kHz   -96 -90 dB
PSR20K RL = 50 Ω, VIN = 3.3 V ± 200 mVPP, f = 20 kHz   -85 -81 dB
THD200_MIC Total harmonic distortion RS=600Ω, RL=600Ω, VIN=1.8V±200mVPP, f=20HZ~20kHz; TA = 25°C; VCC = 3.3 V   0.006   %
THD500_MIC Total harmonic distortion RS=600Ω, RL=600Ω, VIN=1.8V±500mVPP, f=20Hz~20kHz; TA = 25°C; VCC = 3.3 V   0.003   %
XTALK_MICGND Crosstalk between MIC and AGND VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω; TA = 25°C;   -110 -90 dB
ISOOFF_MICGND OFF isolation VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω; TA = 25°C;   -73 -67 dB