SNLS696A April 2021 – May 2021 TSER953
|7:0||SCL_LOW_TIME||R/W||0x7F||I2C SCL Low Time. |
This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 38.1 ns for the nominal oscillator clock frequency of 26.25 MHz. The default value is set to provide a minimum 5-µs SCL low time with the internal oscillator clock running at 26.25 MHz. Delay includes 5 additional clock periods.
Min_delay = 38.0952 ns × (SCL_LOW_TIME + 5)