SNLS696A April 2021 – May 2021 TSER953
Circuit board layout and stack-up for the V3Link devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high-frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference. External bypassing should be low-ESR ceramic capacitors with high-quality dielectric. The voltage rating of the ceramic capacitors must be at least 2× the power supply voltage being used.
TI recommends surface-mount capacitors due to their smaller parasitics. When using multiple capacitors per supply pin, place the smaller value closest to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 47-µF to 100-µF range, which smooths low-frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane. TI also recommends that the user place a via on both ends of the capacitors. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. The small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin description tables typically provide guidance on which circuit blocks are connected to which power pin pairs (see Section 5 for more information). In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four-layer board with a dedicated ground plane. Place CSI-2 signals away from the single-ended or differential V3Link RX input traces to prevent coupling from the CSI-2 lines to the Rx input lines. A single-ended impedance of 50 Ω is typically recommended for coaxial interconnect, and a differential impedance of 100 Ω is typically recommended for STP interconnect. The closely coupled lines help to ensure that coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.